23.2.201023.2.2010 PB171 Spring 2010PB171 Spring 2010 11 PIC Microcontroller Introduction PICPIC MicrocontrollerMicrocontroller IntroductionIntroduction VojtVojtěěchch KrmKrmííččekek vojtec@vojtec@icsics..munimuni..czcz 23.2.201023.2.2010 PB171 Spring 2010PB171 Spring 2010 22 MicrocontrollerMicrocontroller II AAlsolso MCU orMCU or CC CComputeromputer--onon--aa--chipchip ­­ microprocessormicroprocessor ­­ high integrationhigh integration ­­ low power consumptionlow power consumption ­­ selfself--sufficiency and costsufficiency and cost-- effectivenesseffectiveness UsuallyUsually integrates additionalintegrates additional elementselements ­­ readread--write memory for datawrite memory for data storagestorage ­­ readread--only memory, such asonly memory, such as flash for code storageflash for code storage ­­ EEPROM for permanent dataEEPROM for permanent data storagestorage ­­ peripheral devicesperipheral devices andand input/output interfacesinput/output interfaces CClock speeds oflock speeds of a few MHza few MHz,, but this is adequate for typicalbut this is adequate for typical applicationsapplications FFrequentlyrequently used inused in automatically controlledautomatically controlled products and devicesproducts and devices ­­ automobile engine controlautomobile engine control systems, remote controls,systems, remote controls, office machines, appliances,office machines, appliances, power tools, and toyspower tools, and toys 23.2.201023.2.2010 PB171 Spring 2010PB171 Spring 2010 33 MicrocontrollerMicrocontroller -- AchitectureAchitecture VonVon--NeumanNeuman ArchitecureArchitecure ­­ single "data" bus that is used to fetch both instructions and dasingle "data" bus that is used to fetch both instructions and datata ­­ pprogramrogram instructions and data are stored in a common maininstructions and data are stored in a common main memorymemory ­­ wwhen such a controller addresses main memory, it first fetcheshen such a controller addresses main memory, it first fetches an instruction, and then it fetches the data to support thean instruction, and then it fetches the data to support the instruction (if such data is needed).instruction (if such data is needed). Harvard ArchitectureHarvard Architecture ­­ separate data bus and an instruction busseparate data bus and an instruction bus ­­ data and instructions are stored into separate memories that aredata and instructions are stored into separate memories that are accessed separatelyaccessed separately 23.2.201023.2.2010 PB171 Spring 2010PB171 Spring 2010 44 MicocontrollerMicocontroller ­­ CISCCISC andand RISCRISC Complex Instruction Set Computer (CISC)Complex Instruction Set Computer (CISC) ­­ a large set of instructions that can perform complex tasksa large set of instructions that can perform complex tasks ­­ e.g.e.g. the Intel 80X86 series, Thethe Intel 80X86 series, The ZilogZilog Z80, 8051, 6HC11 etc.Z80, 8051, 6HC11 etc. ­­ ffeatureseatures many instructions, addressing modes and takes moremany instructions, addressing modes and takes more than 1 internal clock cycle to executethan 1 internal clock cycle to execute Reduced Instruction Set Computer (RISC)Reduced Instruction Set Computer (RISC) ­­ aa quite small set of instructions which carries out less task perquite small set of instructions which carries out less task per commandcommand ­­ complicated operations are carried out by combining manycomplicated operations are carried out by combining many simple instructionssimple instructions ­­ eexamplesxamples include usage in ARM, SPARC, Atmel AVR MIPS,include usage in ARM, SPARC, Atmel AVR MIPS, PowerPCPowerPC, PIC, PIC 23.2.201023.2.2010 PB171 Spring 2010PB171 Spring 2010 55 PICPIC MicrocontrollerMicrocontroller Harvard architecture microcontrollers byHarvard architecture microcontrollers by Microchip TechnologyMicrochip Technology "Programmable Interface Controller""Programmable Interface Controller" oror "Programmable Intelligent Computer"Programmable Intelligent Computer,,,, PopularPopular duedue toto low cost, wide availability, largelow cost, wide availability, large user base, extensive collection of applicationuser base, extensive collection of application notes, low cost or free development tools, serialnotes, low cost or free development tools, serial programmingprogramming,, rere--programming with flashprogramming with flash memory capabilitymemory capability 23.2.201023.2.2010 PB171 Spring 2010PB171 Spring 2010 66 CoreCore ArchitectureArchitecture II separate code and data spaces (Harvard architecture)separate code and data spaces (Harvard architecture) a small number of fixed length instructionsa small number of fixed length instructions (RISC(RISC architecturearchitecture)) most instructions are single cycle execution (4 clock cycles)most instructions are single cycle execution (4 clock cycles) a single accumulator (W)a single accumulator (W) a hardware stack for storing return addressesa hardware stack for storing return addresses a fairly small amount of addressable data space (typically 256a fairly small amount of addressable data space (typically 256 bytes), extended through bankingbytes), extended through banking data space mapped CPU, portdata space mapped CPU, portss, and peripheral registers, and peripheral registers the program counter is also mapped into the data space andthe program counter is also mapped into the data space and writablewritable no distinction between "memory" and "register" space because theno distinction between "memory" and "register" space because the RAM serves the job of both memory and registersRAM serves the job of both memory and registers 23.2.201023.2.2010 PB171 Spring 2010PB171 Spring 2010 77 CoreCore ArchitectureArchitecture IIII DataData spacespace ­­ RAMRAM CodeCode SpaceSpace -- EPROM, ROM,EPROM, ROM, oror flashflash ROMROM HardwareHardware stackstack ConstantConstant interruptinterrupt latencylatency 35 to 7035 to 70 intructionsintructions, skip, skip intructionintruction,, conditionalconditional executionexecution,, branchingbranching 23.2.201023.2.2010 PB171 Spring 2010PB171 Spring 2010 88 ProgrammingProgramming Only a single accumulatorOnly a single accumulator A small instruction setA small instruction set SSomeome instructions can address RAM and/or immediate constants,instructions can address RAM and/or immediate constants, while others can only use the accumulatorwhile others can only use the accumulator DDirectirect referencreferencinging ofof mmeemorymory in arithmetic and logic operationsin arithmetic and logic operations RegisterRegister--bank switching is required to access the entirebank switching is required to access the entire RAMRAM Conditional skip instructions are used instead of conditional brConditional skip instructions are used instead of conditional branchanch instructionsinstructions WideWide rangerange ofof devicedevice programmersprogrammers ((wewe willwill use PIC PRESTO)use PIC PRESTO) Microchip provides a freeware IDE package called MPLAB, whichMicrochip provides a freeware IDE package called MPLAB, which includes an assembler, linker, software simulator, and debuggerincludes an assembler, linker, software simulator, and debugger 23.2.201023.2.2010 PB171 Spring 2010PB171 Spring 2010 99 FamilyFamily CoreCore ArchitecturalArchitectural DifferencesDifferences BaselineBaseline CoreCore DevicesDevices -- PIC10 series, as well as some PIC12 and PIC16 devicesPIC10 series, as well as some PIC12 and PIC16 devices ­­ 1212--bit wide code memory, and a tiny two level deep call stackbit wide code memory, and a tiny two level deep call stack MidMid--RangeRange CoreCore DevicesDevices -- PIC12PIC12 andand PIC16PIC16 ­­ 1414--bit wide code memory, and 8 level deep call stackbit wide code memory, and 8 level deep call stack PIC17 High End Core DevicesPIC17 High End Core Devices ­­ notnot soso popularpopular,, supressedsupressed by PIC18by PIC18 architecturearchitecture ­­ a memory mapped accumulatora memory mapped accumulator,, read access to code memory (table reads)read access to code memory (table reads),, direct register todirect register to register moves (prior cores needed to move registers through theregister moves (prior cores needed to move registers through the accumulator)accumulator) ­­ an external program memory interface to expand the code spacean external program memory interface to expand the code space ­­ an 8bit x 8bit hardwarean 8bit x 8bit hardware multipliemultiplier,r, a second indirect register paira second indirect register pair PIC18 High End Core DevicesPIC18 High End Core Devices ­­ much deeper call stack (31 levels deep)much deeper call stack (31 levels deep) ­­ the call stack may be read and writtenthe call stack may be read and written ­­ conditional branch instructionsconditional branch instructions ­­ indexed addressing mode (PLUSW)indexed addressing mode (PLUSW) ­­ extending the FSR registers to 12 bits, allowing them to linearlextending the FSR registers to 12 bits, allowing them to linearly address the entire datay address the entire data address spaceaddress space ­­ the addition of another FSR register (bringing the number up tothe addition of another FSR register (bringing the number up to 3)3) PIC24 andPIC24 and dsPICdsPIC 1616--bit Microcontrollersbit Microcontrollers PIC32MX 32PIC32MX 32--bit Microcontrollersbit Microcontrollers 23.2.201023.2.2010 PB171 Spring 2010PB171 Spring 2010 1010 What do the numbers and prefixWhat do the numbers and prefix stands for?stands for? prefix 12 is for chips with 8 pinsprefix 12 is for chips with 8 pins prefix 16 is for 12prefix 16 is for 12--bit and 14bit and 14--bit core chips with more than 8 pinsbit core chips with more than 8 pins prefix 18 is for 16prefix 18 is for 16--bit core chipsbit core chips the letter after number tells the memory type: C is for EPROM (Othe letter after number tells the memory type: C is for EPROM (OTPTP or windowed (except 16C84 that has EEPROM), F is for flash chipsor windowed (except 16C84 that has EEPROM), F is for flash chips and JW is for chips that have windowed EPROM (UV erasable)and JW is for chips that have windowed EPROM (UV erasable) The number (2 or 3 digits) after this letter identifies specificThe number (2 or 3 digits) after this letter identifies specific chipchip versionversion Improved new version of certain PIC types are identified byImproved new version of certain PIC types are identified by appending an A to the type (A chips are in most aspects identicaappending an A to the type (A chips are in most aspects identical tol to their nontheir non--A predecessors, but there can be some differences usuallyA predecessors, but there can be some differences usually on chip programming)on chip programming)