University of Massachusetts Amherst
ECE232: Hardware Organization and Design
Part 3: Verilog Tutorial
http ://www. ecs. u mass. ed u/ece/ece232/
Basic Verilog
module <module_name>  (<module_terminal_list>); <module terminal definitions>
<functionality_of_module> endmodule
Engin 112 Verilog examples:
http://www.ecs.umass.edu/ece/engin112/labs/lab-E2-F09.html http://www.ecs.umass.edu/ece/engin112/labs/lab-E3-F09.html
ECE 353 - Verilog Resources
http://www.ecs.umass.edu/ece353/verilog/verilog.html
ECE 667 Verilog (on the left side menu): http://www.ecs.umass.edu/ece/labs/vlsicad/ece667/ece667.html
http://www.asic-world.com/examples/verilog/index.html
ece 232 Verilog tutorial
1
Full Adder
module FullAdder(a,b,cin,cout,sum); input a, b,  cin;      // inputs output cout,  sum;    // output wire wl, w2, w3, w4;  // internal nets
cout
sum
xor #(10)   (wl,  a, b);  // delay time of 10 units xor #(10)   (sum, wl, cin); and #(8)   (w2, a, b); and #(8)   (w3,  a, cin); and # (8)   (w4, b,  cin) ;
or #(10,  8)(cout, w2, w3, w4);  //   (rise time of 10,  fall 8) endmodule
ece 232_Verilog tutorial_3
Multiple ways of implementing Full Adder
module FullAdder(a,b,cin,sum,cout); input a,b,cin; output sum,  cout;
reg sum, cout;  // registers retain value
always @   (a or b or cin)  // Anytime a or b or cin
CHANGE,  run the
process
begin sum <= a A b A cin; cout <=  (a & b)   |   (a & cin)   |   (b & cin); end endmodule
concurrent assignment
blocking assignment, non-blocking assignments
ece 232_Verilog tutorial_4
Ripple Carry Adder
4-bit Adder
module adder4(A,  B,  ein,  S,  cout); input [3:0]  A, B; input ein; output[3:0] S; output cout; wire cl,  c2, c3;
// 4 instantiated 1-bit Full Adders
FullAdder faO(A[0], B[0],  ein,  cl, S[0]);
FullAdder fal(A[l], B[l],  cl,  c2, S[l]);
FullAdder fa2(A[2], B[2],  c2,  c3, S[2]);
FullAdder fa3(A[3], B[3], c3, cout, S[3]); endmodule
Verilog tutorial
HDL Overview
Hardware description languages (HDL) offer a way to design circuits using text-based descriptions
HDL describes hardware using keywords and expressions.
• Representations for common forms
Logic expressions, truth tables, functions, logic gates
• Any combinational or sequential circuit HDLs have two objectives
• Allow for testing/verification using computer simulation
» Includes syntax for timing, delays
• Allow for synthesis
» Synthesizable HDL
• The two forms often differ!
• We will use synthesizable subset of verilog Two primary hardware description languages
VHDL
• Verilog
232_Verilog tutorial_
Hardware Description Language - Verilog
Represents hardware structure and behavior Logic simulation: generates waveforms
//HDL Example 1
module smpl_circuit(A,B,C,x,y); c input A,B,C; output x,y; wire e;
and gl(e,A,B); not g2(y,C); or g3(x,e,y); endmodule
•■A.
Detect errors before fabrication
	|0ns       20ns      40ns      60ns      80ns       100ns     120ns     140ns     |160ns 180ns
	1
stimcrct.B	1
slimcicl.C	1
	1                                                           \ /
	: / \
Verilog tutorial
Verilog Keywords and Syntax
° Lines that begin with // are comments (ignored by simulation)
° About 100 keywords in total (keywords are case sensitive)
° module: Building block in Verilog
° Always terminates with endmodule
° module followed by circuit name and port list
° Each port is either an input or output
//HDL Example 2
//
module smpl_circuit(A,B,C,x,y); input A,B,C;
output x,y; _
wire e;
and gl(e,A,B); not g2(y,C); or g3(x,e,y); endmodule
Verilog tutorial
Verilog Statements
Verilog has two basic types of statements
1. Concurrent statements (combinational)
(things are happening concurrently, ordering does not matter)
■ Gate instantiations
and (z, x, y), or (c, a, b), xor (S, x, y), etc.
■ Continuous assignments
assign Z = x&y; c = a|b;S = xAy
2. Procedural statements (sequential) (executed in the order written in the code)
■ always @ - executed continuously when the event is active
always @ (posedge clock)
■ initial - executed only once (used in simulation)
■ if then else statements
ece 232_Verilog tutorial_
wire and gate-level Keywords
• Example of gate instantiation
° wire defines internal circuit connection
° Each gate (and, or, not) defined on a separate line
° Gate I/O includes wires and port values
° Note: each gate is instantiated with a name (e.g., g1)
//HDL Example 2
module smpl_circuit(A,B,C,x,y); input A,B,C; output x,y; wire e;
and gl(e,A,B); not g2(y,C); or g3(x,e,y); endmodule
Verilog tutorial_10
Specifying Boolean Expressions
• Example of continuous assignment //HDL Example 3
//Circuit specified with Boolean equations
module circuit_bln (x,y,A,B,C,D); input A,B,C,D; output x,y;
assign x = A | (B & C) | (~B & C); assign y = (~B & C) | (B & ~C & ~D);
endmodule
° assign keyword used to indicate expression
°  Assignment takes place continuously
°  Note new symbols specific for Verilog
° OR->|
° AND->&
° NOT->~
ece 232_Verilog tutorial_11
User Defined Primitives
//HDL Example 4
//User defined primitive(UDP) primitive crctp (x,A,B,C);
output x;
input A,B,C;
//Truth table for x(A,B,C) = Minterms (0,2,4,6,7) table
//    A B  C : x (Note that this is only a comment) 0  0 0:1; 0  0 1:0; 0   1 0:1;
0 1 1:0; 10 0:1;
1 0 1:0; 110:1; 1   1   1 ■ 1"
___.. '   ' ° Allows definition of truth table
endtable
endprimitive ° Only one output is allowed
Verilog tutorial_12
More Verilog Examples -1
//HDL Example 5
//Dataflow description of a 2-to-4-line decoder
module decoder_df (A,B,E,D); input A,B,E; output [0:3] D;
assign D[0] = ~(~A & ~B & ~E), D[l] = ~(~A&B&~E), D[2] = ~(A&~B&~E), D[3] = ~(A&B&~E); endmodule
° Combinational functionality ° All assignments take place at the same time ° Note declaration of a bus ° output [0:3] D;
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More Verilog Examples - 2
//HDL Example 6
//Dataflow description of a 4-bit comparator.
module mag_comp (A,B,ALTB,AGTB,AEQB); input [3:0] A,B; output ALTB,AGTB,AEQB; assign ALTB = (A < B), AGTB = (A > B), AEQB = (A == B); endmodule
° Easy to define arithmetic functionality
° Each comparison creates a single bit result
° Synthesizer automatically converts RTL description to gate-level description
° RTL = register transfer level
ece 232_Verilog tutorial_14
More Verilog Examples - 3
• Example of sequential assignment //HDL Example 7
//Behavioral description of 2-to-l-line multiplexer
module mux2xl_bh(A,B,select,OUT); input A,B,select; output OUT; reg OUT;
always @ (select or A or B) if (select == 1) OUT = A; else OUT = B; endmodule
° Conditional statements (if, else) allow for output choices
° always keyword used to indicate action based on variable change
° Generally conditional statements lead to multiplexers
ece 232_Verilog tutorial_15
Modeling Circuit Delay
° This is for simulation only (not for synthesis)
° Timescale directive indicates units of time for simulation
° 'timescale 1 ns /10Ops ° #(30) indicates an input to output delay for gate g1 of 30 ns ° #(10) indicates an input to output delay for gate g2 of 10 ns
//HDL Example 2
//
//Description of circuit with delay
module circuit_with_delay (A,B,C,x,y); input A,B,C;
output x,y; A \~Py
wire e; B and #(30) gl(e,A,B); or #(20) g3(x,e,y); c not #(10) g2(y,C); endmodule
Verilog tutorial
16
Test bench Stimulus -1
//hdl
//Stimulus for simple circuit
module stimcrct; o
reg A,B,C;
wire x,y;
o
circuit with delay cwd(A,B,C,x,y) ; initial
begin ° A= 1'bO; B = 1'bO;  C = 1'bO; #100
A= l'bl; B = l'bl;  C = l'bl; #100 $finish; end 0 endmodule
//Description of circuit with delay // NOT synthesizable !
module circuit with delay (A,B,C,x,y); input A,B,C; output x,y; wire e;
and #(30) gl(e,A,B) ; or #(20) g3(x,e,y); not #(10) g2(y,C);
ECEgndmodul6_Verilog tutorial
Module circuit_with_delay is instantiated
reg keyword indicates that values are stored (driven)
Stimulus signals are applied sequentially
$finish indicates simulation should end
Result: collection of waveforms
17
Test bench Stimulus - 2
	Ons       |20ns       |40ns       |60ns       80ns       1100ns      120ns     |140ns     1160ns |180ns I I I I 1 i I I I 1 I i I I  1 I I I I  1 I i I I 1 i i I i 1 I I I I 1  I i i I 1 I i i i  1  i I I I
stimcrct.A	/
stimcrct.B	/
stimcrct. C	/
stimcrct. x	
	;     /                    \ i
stimcrct,y	
	: / \
Timescale directive indicates A units of time for simulation b
° 'timescale 1 ns /10Ops
Note that input values change at 100ns
Shaded area at left indicates output values are undefined
Verilog tutorial_18
Modeling Sequential Elements
module D-latch (D, Clk, Q);
input D, Clk; output Q; reg Q;
always @(D or Clk) if (Clk)
Q = D;
endmodule
ClkfJ
D Latch
Q$latch
	PRE D Q ENA CLR	
		
		
Verilog tutorial
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Verilog - D Flip-flop
module D-flipflop (D, Clk, Q);
input D, Clk; output Q; reg Q;
always @(posedge Clk) Q = D;
endmodule
dLZZ>-
Clkl >-
OregO
	PRE D Q > ENA CLR	
		
		
>Q
Verilog tutorial
20
Verilog - Blocking Assignment (=)
module DFF-blocking(D, Clock, Ql, Q2);
input D, Clock; output Ql, Q2; reg Ql, Q2;
d
Clock
always @(posedge Clock) begin
// blocking assignment - series execution
Ql = D; Q2 = Ql;
end
endmodule
Q1~reg0
PRE d c
>
ena
or
Q2~reg0
pre d c
>
ena or
>Q1
>Q2
Verilog tutorial
21
Verilog - Non-blocking Assignment (<=)
module DFF-non-blocking(D, Clock, Ql, Q2); input D, Clock; output Ql, Q2; reg Ql, Q2;
always @(posedge Clock) begin
// non blocking assignment - can be done in parallel (or any order) Ql <= D;
Q2 <= Ql; _
end
D
Clock
endmodule
PRE D Q
ENA CLR
ENA CLR
Verilog tutorial
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Verilog - D Flip-flop with Reset
• D flip-flop with asynchronous reset (asserted negative)
module dff_reset(D, Clock, Resetn, Q); input D, Clock, Resetn; output Q; reg Q;
Clock)
always @(negedge Resetn or posedge
if (!Resetn)
Q <= 0;
else
Q <= D;
endmodule
D
Clock
Resetn[ Verilog tutorial
OregO		
	PRE D C > ENA cm	
		
		
23
Finite State Machines -1
Mealy FSM
• Output based on present state and input
• Output changes during transition
in/out
present state i—
■f—*- outputs
next state
Moore FSM
• Output based on state only
• Output is associated with state
(si/
?ut
2P out2>
inputs -
CL
present state'
FFs
^ CL
next state
■outputs
Verilog tutorial
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Finite State Machines - 2
State diagrams are representations of Finite State Machines (FSM)
Mealy FSM
• Output depends on input and state
• Output is not synchronized with clock
» can have temporarily unstable output
Moore FSM
• Output depends only on state
Verilog tutorial
Example 1: Sequence Detector
■ Circuit specification:
• Design a circuit that outputs a 1 when three consecutive 1's have been received as input and 0 otherwise.
■ FSM type
• Moore or Mealy FSM?
» Both possible
» Chose Moore to simplify diagram
■ State diagram:
» State SO: zero 1s detected » State S1: one 1 detected » State S2: two 1s detected » State S3: three 1s detected
ece 232_Verilog tutorial_26
Sequence Detector: Verilog (Moore FSM)
module seq3_detect_moore(x,clk, y);
// Moore machine for a three-Is sequence detection
input x, elk;
output y;
reg [1:0] state;
parameter S0=2'b00, Sl = 2'b01, S2=2'bl0, S3=2'bll;
// Define the sequential block always @(posedge elk) case (state)
SO: if (x) state <= SI;
else     state <= SO; SI: if (x) state <= S2;
else     state <= SO; S2: if (x) state <= S3;
else     state <= SO; S3: if (x) state <= S3;
else     state <= SO;
endcase // Define output during S3
assign y = (state == S3); endmodule
Verilog tutorial
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Sequence Detector: FSM Synthesis + Simulation Synthesized Moore FSM (Quartus)
■ Simulation results (Quartus)
			1  1 ;			..........................i.......       ji p1"""""^		' """""			—         1................ -		
													
	■												
							. .... -   .                 :PV''''^i ■						
Verilog tutorial
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Sequence Detector: Verilog (Mealy FSM)
module seq3_detect_mealy(x,clk, y);
// Mealy machine for a three-Is sequence detection
input x, elk;
output y;
reg y;
reg [1:0] pstate, nstate;   //present and next states parameter S0=2'b00, Sl=2'b01, S2=2'bl0, S3=2'bll; // Next state and output combinational logic // Use blocking assignments "=" always @(x or pstate) case (pstate)
SO: if (x) begin nstate = SI;
else begin nstate SI: if (x) begin nstate = S2;
else begin nstate S2: if (x) begin nstate = S3;
else begin nstate S3: if (x) begin nstate = S3; else begin nstate
endcase
// Sequential logic, use nonblocking assignments "< = always @(posedge elk)
pstate <= nstate;
endmodule
ece 232_Verilog tutorial_
0/0 __o/o
Uso>^o^sn
y = 0; SO; y :
end 0; end y = 0; end = SO; y = 0; end y = 0; end = SO; y = 0; end y = 1; end = SO; y = 0; end
29
Sequence Detector: FSM Synthesis + Simulation Synthesized Mealy FSM (Quartus)
pstate
y~0
■ Simulation results (Quartus)
elk			1					1					1					1					1					1					1				l|	1			r-
X																																									
V																							1																		
psIatE	I'			P	>l =	:e	S			rc=	to	s:	X				ps	a:	e.I	3								= '		a			X	p		te	Sljfp	E.atE.32)	-	state	
																																									
ece 232_Verilog tutorial_30
Example 2: Vending Machine FSM - 1
Specify the Problem
• Deliver package of gum after 15 cents deposited
• Single coin slot for dimes, nickels
• No change
• Design the FSM using combinational logic and flip flops
Coin Sensor	N	Vending Machine FSM		
	D		Open	Gum Release Mechanism
				
	Reset			
	-^			
Clk
Verilog tutorial
31
Example 2: Vending Machine FSM - 2
State diagram
ResetSf^V
Reuse states whenever possible
Present	Inputs		Next	Output
State	D	N	State	Open
0$	0	0	0$	0
	0	1	5$	0
	1	0	10$	0
	1	1	X	X
5$	0	0	5$	0
	0	1	10$	0
	1	0	15$	0
	1	1	X	X
10$	0	0	10$	0
	0	1	15$	0
	1	0	15$	0
	1	1	X	X
15$	X	X	15$	1
Symbolic State Table |
Verilog tutorial
32
Vending Machine: Verilog (Moore FSM)
module vending_moore(N, D, elk, reset, open); // Moore FSM for a vending machine
input N, D, elk, reset; Synthesizing Moore FSM directly from state diagram
output open;
reg [1:0] state;
parameter S0=2'b00, S5=2'b01, S10=2'bl0, S15=2'bll;
// Define the sequential block always @(posedge reset or posedge elk) if (reset) state <= SO; else case (state)
SO: if (N) state <= S5;
else if (D) state <= S10; else state <= SO; S5: if (N) state <= S10;
else if (D) state <= S15; else state <= S5; S10: if (N) state <= S15;
else if (D) state <= S15; else state <= S10; S15: state <= S15; endcase // Define output during S3
assign open = (state == S15); endmodule
N=l
N,D=x
Verilog tutorial
33
Vending Machine: Verilog (Mealy FSM)
module vending_mealy(IM, d, elk, reset, open); // Mealy FSM for a vending machine
input n, d, elk, reset; Synthesizing Mealy FSM directly from state diagram
output open;
reg [1:0] pstate, nstate;
reg open;
parameter S0=2'b00, S5=2'b01, S10=2'bl0, S15=2'bll; N'&D'/O
// Next state and ouptut combinational logic always @(N or D or pstate or reset) if (reset)
begin nstate = SO; open = 0; end else case (pstate)
SO: begin open = 0; if (N) nstate = S5; else if (D) nstate = S10; else nstate = SO; end S5: begin open = 0; if (N)nstate = S10; else if (D) nstate = S15;
else nstate = S5; end S10: if (N | D) begin nstate = S15; open = 0; end
else begin nstate = S10; open = 0; end S15: begin nstate = SO; open = 1; end endcase
// FF logic, use nonblocking assignments "<=" always @ (posedge elk)
pstate < = nstate;
endmodule
ece 232_Verilog tutorial_34
																										
				Vending Machine: Simulation Results																						
■ Moore FSM																										
	ck																									
	resEt																									
	N																									
	D																									
	state {		la IE.	so	_xl	Elo.S		state		X						a-e S		St		10	X					
	□pen							J	^ ru													J				
■ N		lealy FSM																								
	clk																									
	reset																									
	N																									
	□																									
	p51BtE	<	::-;r.v.::		L*								so		*>								s-«		.SO)	
			—	-	j—			i		1_						-	-	-	-	-	-	i	TU			
ECE 23		2			]—				i	1       1       1       1 1 Verilog tutorial						1-		1-		I—			i—	1—	35	
Summary
■ Hardware description languages provide a valuable tool for computer engineers
■ Any logic circuit (combinational or sequential) can be represented in HDL
■ Circuits created using keywords and syntax
■ Possible to use timing information
• Explicit delay (#) is for simulation purposes only
• Circuits with delays are not synthesizable
■ Gate and RTL descriptions are possible
■ Verilog is widely used in industry
Verilog tutorial
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