Verilog for Finite State Machines
  Strongly recommended style for FSMs
  Works for both Mealy and Moore FSMs
  You can break the rules
  But you have to live with the consequences
Sprint 2010 CSE370 - XV - Verilog for Finite State Machines 1
Spring 2010 CSE370 - XIV - Finite State Machines I 2
Mealy and Moore machines
  Moore
  Mealy
state feedback
inputs
outputsreg
combinational
logic for
next state
logic for
outputs
inputs outputs
state feedback
reg
combinational
logic for
next state
logic for
outputs
state feedback
Constructing State Machines in Verilog
  We need register to hold
  the current state
  always @(posedge clk) block
  We need next state function
  Where do we go from each state given the inputs
  state by state case analysis
  next state determined by current state and inputs
  We need the output function
  State by state analysis
  Moore: output determined by current state only
  Mealy: output determined by current state and inputs
Sprint 2010 CSE370 - XV - Verilog for Finite State Machines 3
State Register
  Declare two values
  state : current state – output of state register
  nxtState : next state – input to state register
  We rely on next state function to give us nxtState
  Declare symbols for states with state assignment
Sprint 2010 CSE370 - XV - Verilog for Finite State Machines 4
localparam IDLE=0, WAITFORB=1,
DONE=2, ERROR=3;
reg [1:0] state, // Current state
nxtState; // Next state
State Register
  Simple code for register
  Define reset state
  Otherwise, just move to nxtState on clock edge
Sprint 2010 CSE370 - XV - Verilog for Finite State Machines 5
localparam IDLE=0, WAITFORB=1,
DONE=2, ERROR=3;
reg [1:0] state, // Current state
nxtState; // Next state
always @(posedge clk) begin
if (reset) begin
state <= IDLE; // Initial state
end else begin
state <= nxtState;
end
end
Next State Function
  Combinational logic function
  Inputs : state, inputs
  Output : nxtState
  We could use assign statements
  We will use an always @(*) block instead
  Allows us to use more complex statements
  if
  case
Sprint 2010 CSE370 - XV - Verilog for Finite State Machines 6
always @(*) Block
  Used for combinational logic functions
  Is always active – like assign statements
  Assignment ( = ) used to assign function value
  Output can be assigned more than once
  e.g. multiple if statements
  The last one counts
  All outputs must be assigned at least once
  No matter how ifs and cases are executed
  Otherwise function is undefined
  Use default assignments to help you
Sprint 2010 CSE370 - XV - Verilog for Finite State Machines 7
Next State Function
  Describe what happens in each state
  Case statement is natural for this
Sprint 2010 CSE370 - XV - Verilog for Finite State Machines 8
always @(*) begin
nxtState = state; // Default next state: don’t move
case (state)
IDLE : begin
if (B) nxtState = ERROR;
else if (A) nxtState = WAITFORB;
end
WAITFORB : begin
if (B) nxtState = DONE;
end
DONE : begin
end
ERROR : begin
end
endcase
end
Output Function
  Describe the output of each state
Sprint 2010 CSE370 - XV - Verilog for Finite State Machines 9
always @(*) begin
nxtState = state; // Default next state: stay where we are
out = 0; // Default output
case (state)
IDLE : begin
if (B) nxtState = ERROR;
else if (A) nxtState = WAITFORB;
end
WAITFORB : begin
if (B) nxtState = DONE;
end
DONE : begin
out = 1;
end
ERROR : begin
end
endcase
end
Example #2 : Edge Detector (Moore)
Sprint 2010 CSE370 - XV - Verilog for Finite State Machines 10
D/1
E/1
B/0
A/0
C/0
1
0
0
0
0
1
1
1
1
0
reset
localparam A=0, B=1, C=2, D=4, E=5;
reg [2:0] state, // Current state
nxtState; // Next state
always @(posedge clk) begin
if (reset) begin
state <= A; // Initial state
end else begin
state <= nxtState;
end
end
Example #2 : Edge Detector (Moore)
Sprint 2010 CSE370 - XV - Verilog for Finite State Machines 11
D/1
E/1
B/0
A/0
C/0
1
0
0
0
0
1
1
1
1
0
reset
always @(*) begin
nxtState = state;
out = 0;
case (state)
A : if (in) nxtState = C;
else nxtState = B;
B : if (in) nxtState = D;
C : if (~in) nxtState = E;
D : begin
out = 1;
if (in) nxtState = C;
else nxtState = E;
end
E : begin
out = 1;
if (in) nxtState = D;
else nxtState = B;
end
default : begin
out = 1’bX;
nxtState = 3’bX;
end
endcase
end
Example #2 : Edge Detector (Moore)
  Using state assignment for output
  Only works for Moore FSM
Sprint 2010 CSE370 - XV - Verilog for Finite State Machines 12
D/1
E/1
B/0
A/0
C/0
1
0
0
0
0
1
1
1
1
0
resetalways @(*) begin
nxtState = state;
out = state[2];
case (state)
A : if (in) nxtState = C;
else nxtState = B;
B : if (in) nxtState = D;
C : if (~in) nxtState = E;
D : if (in) nxtState = C;
else nxtState = E;
E : if (in) nxtState = D;
else nxtState = B;
default : nxtState = 3’bX;
endcase
end
Example #2 : Edge Detector (Mealy)
Sprint 2010 CSE370 - XV - Verilog for Finite State Machines 13
localparam A=0, B=1, C=2;
reg [1:0] state, // Current state
nxtState; // Next state
always @(posedge clk) begin
if (reset) begin
state <= A; // Initial state
end else begin
state <= nxtState;
end
end
B
A
C
0/1
0/0
0/0
1/1
1/0
1/0
reset/0
Example #2 : Edge Detector (Moore)
  Output depends on state and input
Sprint 2010 CSE370 - XV - Verilog for Finite State Machines 14
always @(*) begin
nxtState = state;
out = 0;
case (state)
A : if (in) nxtState = C;
else nxtState = B;
B : if (in) begin
out = 1;
nxtState = C;
end
C : if (~in) begin
out = 1;
nxtState = B;
end
default : begin
out = 1’bX;
nxtState = 3’bX;
end
endcase
end
B
A
C
0/1
0/0
0/0
1/1
1/0
1/0
reset/0
Summary
  Please use “standard” FSM Verilog style shown here
  Do not be beguiled into thinking this is programming C!
  always @(posedge clk) block
  Use only for registers with simple logic
  e.g. shifter, counter, enabled register, etc.
  Miscellaneous combinational logic
  assign statements (always safe)
  always @(*) block (be very careful)
  Think of this as a complex assign statement
  Fine to have more than one
Sprint 2010 CSE370 - XV - Verilog for Finite State Machines 15