library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;


entity adder_4 is
    port (
        in_1: in std_logic_vector(3 downto 0);
        in_2: in std_logic_vector(3 downto 0);

        leds: out std_logic_vector(4 downto 0)
    );
end adder_4;


architecture behavior of adder_4 is
begin

    leds <= std_logic_vector(unsigned(in_1) + unsigned(in_2));

end;