library ieee;
use ieee.std_logic_1164.all;


entity rs is
    port (
        r: in std_logic;
        s: in std_logic;

        q: out std_logic;
        not_q: out std_logic
    );

end rs;


architecture behavior of rs is

    signal wire_q: std_logic;
    signal wire_not_q: std_logic;

begin

    wire_q <= r nor wire_not_q;
    wire_not_q <= s nor wire_q;

    q <= wire_q;
    not_q <= wire_not_q;

end;