J 2016

High-performance forward error correction: Enabling multi-gigabit flows and beyond on commodity GPU and CPU hardware in presence of packet loss

KABÁT, Milan, Vojtěch DAVID, Petr HOLUB and Martin PULEC

Basic information

Original name

High-performance forward error correction: Enabling multi-gigabit flows and beyond on commodity GPU and CPU hardware in presence of packet loss

Authors

KABÁT, Milan (703 Slovakia, belonging to the institution), Vojtěch DAVID (203 Czech Republic, belonging to the institution), Petr HOLUB (203 Czech Republic, guarantor, belonging to the institution) and Martin PULEC (203 Czech Republic)

Edition

Future Generation Computer Systems, Amsterdam, The Netherlands, Elsevier Science, 2016, 0167-739X

Other information

Language

English

Type of outcome

Článek v odborném periodiku

Field of Study

10201 Computer sciences, information science, bioinformatics

Country of publisher

Czech Republic

Confidentiality degree

není předmětem státního či obchodního tajemství

References:

Impact factor

Impact factor: 3.997

RIV identification code

RIV/00216224:14610/16:00087775

Organization unit

Institute of Computer Science

UT WoS

000368383200026

Keywords in English

Graphics processing unit (GPU); Forward error correction; Low-density generation matrix; High-definition video; Low latency transmissions; UltraGrid

Tags

Tags

Reviewed
Změněno: 27/4/2018 13:03, Mgr. Alena Mokrá

Abstract

V originále

In demanding real-time multimedia transmissions, even a small packet loss might significantly degrade the visual quality. As retransmission is not an option in real-time transfers especially when transmitting the data over long distances, it is necessary to employ mechanisms of Forward Error Correction (FEC). Low-Density Generator Matrix (LDGM) codes are known to be suitable for coding on large block sizes, however, high bitrates of currently used video formats (FullHD, 4K) also require high throughput of FEC coding and decoding. We propose a parallel design of LDGM encoding and decoding algorithms suitable for off-the-shelf, (massively) parallel platforms, such CPUs with vector units or GPUs, and evaluate our approach in real-world scenarios of high-definition and 4K video transmissions. Our results show that offloading FEC computation to such platform is beneficial for low-latency, high-quality multimedia transmissions and may even enable transmissions beyond 10Gbps once the commodity network interfaces reach this speed.

Links

GAP202/12/0306, research and development project
Name: Dyschnet - Dynamické plánování a rozvrhování výpočetních a síťových zdrojů (Acronym: Dyschnet)
Investor: Czech Science Foundation