Efficient On-Chip Randomness Testing Utilizing Machine Learning Techniques.

MRAZEK, Vojtech, Lukas SEKANINA, Roland DOBAI, Marek SÝS a Petr ŠVENDA. Efficient On-Chip Randomness Testing Utilizing Machine Learning Techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. IEEE, 2019, roč. 27, č. 12, s. 2734-2744. ISSN 1063-8210. Dostupné z: https://dx.doi.org/10.1109/TVLSI.2019.2923848.

Základní údaje

• Originální název: Efficient On-Chip Randomness Testing Utilizing Machine Learning Techniques.
• Autoři: MRAZEK, Vojtech, Lukas SEKANINA, Roland DOBAI, Marek SÝS (703 Slovensko, garant, domácí) a Petr ŠVENDA (203 Česká republika, domácí).
• Vydání: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, IEEE, 2019, 1063-8210.

Další údaje

• Originální jazyk: angličtina
• Typ výsledku: Článek v odborném periodiku
• Obor: 10201 Computer sciences, information science, bioinformatics
• Stát vydavatele: Spojené státy
• Utajení: není předmětem státního či obchodního tajemství
• WWW: URL
• Impakt faktor: Impact factor: 2.037
• Kód RIV: RIV/00216224:14330/19:00107545
• Organizační jednotka: Fakulta informatiky
• Doi: http://dx.doi.org/10.1109/TVLSI.2019.2923848
• UT WoS: 000508360300004
• Klíčová slova anglicky: Testing; Cryptography; Field programmable gate arrays; Hardware; System-on-chip; Generators; Machine learning
• Příznaky: Mezinárodní význam, Recenzováno

Anotace

Randomness testing is an important procedure that bit streams, produced by critical cryptographic primitives such as encryption functions and hash functions, have to undergo. In this paper, a new hardware platform for the randomness testing is proposed. The platform exploits the principles of genetic programming, which is a machine learning technique developed for the automated program and circuit design. The platform is capable of evolving efficient randomness distinguishers directly on a chip. Each distinguisher is represented as a Boolean polynomial in the algebraic normal form. The randomness testing is conducted for bit streams that are either stored in an on-chip memory or generated by a circuit placed on the chip. The platform is developed with a Xilinx Zynq-7000 All Programmable System on Chip that integrates a field programmable gate array with on-chip ARM processors. The platform is evaluated in terms of the quality of randomness testing, performance, and resources utilization. With power budget less than 3 W, the platform provides comparable randomness testing capabilities with the standard testing batteries running on a personal computer.

Návaznosti

• GA16-08565S, projekt VaV: Název: Rozvoj kryptoanalytických metod prostřednictvím evolučních výpočtů

Investor: Grantová agentura ČR, Advancing cryptanalytic methods through evolutionary computing