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    2004

    1. How to Formalize FPGA Hardware Design
      HOLEČEK, Jan, Tomáš KRATOCHVÍLA, Vojtěch ŘEHÁK, David ŠAFRÁNEK and Pavel ŠIMEČEK. How to Formalize FPGA Hardware Design. Praha: CESNET, z.s.p.o., 2004. CESNET Technical Report No. 04/2004.
      More: https://is.muni.cz/publication/559201/en
    2. Verification Process of Hardware Design in Liberouter Project
      HOLEČEK, Jan, Tomáš KRATOCHVÍLA, Vojtěch ŘEHÁK, David ŠAFRÁNEK and Pavel ŠIMEČEK. Verification Process of Hardware Design in Liberouter Project. Praha: CESNET z.s.p.o., 2004. CESNET Technical Report No. 05/2004.
      More: https://is.muni.cz/publication/561408/en
    3. Verification Results in Liberouter Project
      HOLEČEK, Jan, Tomáš KRATOCHVÍLA, Vojtěch ŘEHÁK, David ŠAFRÁNEK and Pavel ŠIMEČEK. Verification Results in Liberouter Project. Praha: CESNET, z.s.p.o., 2004. CESNET Technical Report No. 03/2004.
      More: https://is.muni.cz/publication/558042/en

    2003

    1. Verification of COMBO6 VHDL Design
      KRATOCHVÍLA, Tomáš, Vojtěch ŘEHÁK and Pavel ŠIMEČEK. Verification of COMBO6 VHDL Design. Praha: CESNET, z.s.p.o., 2003. CESNET Technical Report No. 17/2003.
      More: https://is.muni.cz/publication/490367/en
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