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BEYER, Dirk and Jan STREJČEK. Case Study on Verification-Witness Validators: Where We Are and Where We Go. In Gagandeep Singh, Caterina Urban. Static Analysis - 29th International Symposium, SAS 2022, Auckland, New Zealand, December 5–7, 2022, Proceedings. Cham (Switzerland): Springer, 2022. p. 160-174. ISBN 978-3-031-22307-5. doi:10.1007/978-3-031-22308-2_8.
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CHALUPA, Marek and Jan STREJČEK. Backward Symbolic Execution with Loop Folding. In Cezara Dragoi, Suvam Mukherjee, and Kedar S. Namjoshi. Static Analysis - 28th International Symposium, SAS 2021, Chicago, IL, USA, October 17-19, 2021, Proceedings. Cham (Switzerland): Springer, 2021. p. 49-76. ISBN 978-3-030-88805-3. doi:10.1007/978-3-030-88806-0_3.
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CHALUPA, Marek, Tomáš JAŠEK, Jakub NOVÁK, Anna ŘECHTÁČKOVÁ, Veronika ŠOKOVÁ and Jan STREJČEK. Symbiotic 8: Beyond Symbolic Execution. In Jan Friso Groote, Kim Guldstrand Larsen. Tools and Algorithms for the Construction and Analysis of Systems - 27th International Conference, TACAS 2021, Held as Part of the European Joint Conferences on Theory and Practice of Software, ETAPS 2021, Luxembourg City, Luxembourg, March 27 - April 1, 2021, Proceedings, Part II. Cham (Švýcarsko): Springer, Cham, 2021. p. 453-457. ISBN 978-3-030-72012-4. doi:10.1007/978-3-030-72013-1_31.
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CHALUPA, Marek, Jan STREJČEK and Martina VITOVSKÁ. Joint Forces for Memory Safety Checking Revisited. International Journal on Software Tools for Technology Transfer (STTT). Springer, 2020, vol. 22, No 2, p. 115-133. ISSN 1433-2779. doi:10.1007/s10009-019-00526-2.
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CHALUPA, Marek and Jan STREJČEK. Evaluation of Program Slicing in Software Verification. In Wolfgang Ahrendt, Silvia Lizeth Tapia Tarifa. Integrated Formal Methods - 15th International Conference, IFM 2019, Bergen, Norway, December 2-6, 2019, Proceedings. Cham (Switzerland): Springer, 2019. p. 101-119. ISBN 978-3-030-34967-7. doi:10.1007/978-3-030-34968-4_6.
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BAIER, Christel, František BLAHOUDEK, Alexandre DURET-LUTZ, Joachim KLEIN, David MÜLLER and Jan STREJČEK. Generic Emptiness Check for Fun and Profit. In Yu-Fang Chen, Chih-Hong Cheng, Javier Esparza. Automated Technology for Verification and Analysis - 17th International Symposium, ATVA 2019, Taipei, Taiwan, October 28-31, 2019, Proceedings. Cham (Switzerland): Springer, 2019. p. 445-461. ISBN 978-3-030-31783-6. doi:10.1007/978-3-030-31784-3_26.
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CHALUPA, Marek, Martina VITOVSKÁ and Jan STREJČEK. Symbiotic 5: Boosted Instrumentation (Competition Contribution). In Dirk Beyer and Marieke Huisman. Tools and Algorithms for the Construction and Analysis of Systems, 24th International Conference, Proceedings, Part II. Berlin: Springer, 2018. p. 442-446. ISBN 978-3-319-89963-3. doi:10.1007/978-3-319-89963-3_29.
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CoIn Tool Set (software)
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BENEŠ, Nikola, Luboš BRIM, Ivana ČERNÁ, Jiří SOCHOR, Pavlína VAŘEKOVÁ and Barbora ZIMMEROVÁ. Partial Order Reduction for State/Event LTL. In Proceedings of the International Conference on Integrated Formal Methods (IFM'09). Berlin / Heidelberg, Germany: Springer Verlag, 2009. p. 307-321. ISBN 978-3-642-00254-0. doi:10.1007/978-3-642-00255-7_21.
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BENEŠ, Nikola, Ivana ČERNÁ, Jiří SOCHOR, Pavlína VAŘEKOVÁ and Barbora ZIMMEROVÁ. A Case Study in Parallel Verification of Component-Based Systems. In Pre-proceedings of the Workshop on Parallel and Distributed Methods in verifiCation (PDMC'08). Budapest, Hungary: ETAPS, 2008. p. 35-51. ISSN 1571-0661.
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BENEŠ, Nikola, Ivana ČERNÁ, Jiří SOCHOR, Pavlína MORAVCOVÁ VAŘEKOVÁ and Barbora BÜHNOVÁ. A Case Study in Parallel Verification of Component-Based Systems. Electronic Notes in Theoretical Computer Science. Neuveden: Elsevier, 2008, vol. 220, No 2, p. 67-83, 16 pp. ISSN 1571-0661.
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MORAVCOVÁ VAŘEKOVÁ, Pavlína, Ivana VAŘEKOVÁ and Ivana ČERNÁ. Automated Computing of the Maximal Number of Handled Clients for Client-Server Systems. In Proceedings of the International Workshop on Formal Aspects of Component Software (FACS'08). Málaga, Spain: Department of Computer Science, University of Málaga, 2008. p. 41-55. ISSN 1571-0661.
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VAŘEKOVÁ, Pavlína, Barbora ZIMMEROVÁ, Pavel MORAVEC and Ivana ČERNÁ. Formal verification of systems with an unlimited number of components. IET Software journal. Inst. of Engeneering and Technology, 2008, Volume 2, Isuue 6, p. p. 532-546, 15 pp. ISSN 1751-8806.
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MORAVCOVÁ VAŘEKOVÁ, Pavlína and Ivana ČERNÁ. Model Checking of Control-User Component-Based Parametrised Systems. In Lecture Notes in Computer Science 5282. Germany: Springer Verlag, 2008. p. 146-162. ISBN 978-3-540-87890-2.
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BENEŠ, Nikola, Luboš BRIM, Ivana ČERNÁ, Jiří SOCHOR, Pavlína VAŘEKOVÁ and Barbora ZIMMEROVÁ. Partial Order Reduction for State/Event LTL. Brno, Czech Republic: Faculty of Informatics, Masaryk University, 2008. 21 pp. Technical report FIMU-RS-2008-07.
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BENEŠ, Nikola, Luboš BRIM, Ivana ČERNÁ, Jiří SOCHOR, Pavlína VAŘEKOVÁ and Barbora ZIMMEROVÁ. The CoIn Tool: Modelling and Verification of Interactions in Component-Based Systems. In Pre-proceedings of the International Workshop on Formal Aspects of Component Software (FACS'08). Málaga, Spain: Department of Computer Science, University of Málaga, 2008. p. 221-225. ISSN 1571-0661.
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VAŘEKOVÁ, Pavlína, Pavel MORAVEC, Ivana ČERNÁ and Barbora ZIMMEROVÁ. Effective verification of systems with a dynamic number of components. In Proceedings of the 2007 conference on Specification and verification of component-based systems: 6th Joint Meeting of the European Conference on Software Engineering and the ACM SIGSOFT Symposium on the Foundations of Software Engineering. New York, NY, USA: ACM Press, 2007. p. 3-13. ISBN 978-1-59593-721-6.
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BABICA, Jindřich, Vojtěch ŘEHÁK, Petr SLOVÁK, Pavel TROUBIL and Martin ZAVADIL. Formalisms and Tools for Design and Specification of Network Protocols. Brno: FI MU, 2007. FIMU-RS-2007-02.
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SMRČKA, Aleš, Vojtěch ŘEHÁK, Tomáš VOJNAR, David ŠAFRÁNEK, Petr MATOUŠEK and Zdeněk ŘEHÁK. Verifying VHDL Designs with Multiple Clocks in SMV. In Formal Methods Applications and Technology, 11th International Workshop on Formal Methods for Industrial Critical Systems, FMICS 2006, and 5th International Workshop on Parallel and Distributed Methods in Verification, PDMC 2006. Bonn: Springer-Verlag, 2007. p. 148-164, 16 pp. ISBN 978-3-540-70951-0.
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KUČERA, Antonín and Petr JANČAR. Equivalence-Checking on Infinite-State Systems: Techniques and Results. Theory and practice of logic programming. Cambridge: Cambridge University Press, 2006, vol. 6, No 3, p. 227-264. ISSN 1471-0684.
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KRATOCHVÍLA, Tomáš, Vojtěch ŘEHÁK and David ŠAFRÁNEK. Formal Verification of a FIFO Component in Design of Network Monitoring Hardware. In 10 years of CESNET - CESNET CONFERENCE 2006. Praha: CESNET, z.s.p.o., 2006. p. 151-160. ISBN 978-80-239-6533-9.
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SMRČKA, Aleš, Petr HLÁVKA, David ŠAFRÁNEK, Vojtěch ŘEHÁK, Pavel ŠIMEČEK and Tomáš VOJNAR. Formal Verification of the CRC Algorithm Properties. In Proceedings of 2nd Doctoral Workshop on Mathematical and Engineering Methods in Computer Science (MEMICS 2006). Brno: FIT BUT, 2006. p. 55-62. ISBN 80-214-3287-X.
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ŠAFRÁNEK, David, Vojtěch ŘEHÁK, Tomáš KRATOCHVÍLA, Pavel ŠIMEČEK, Petr HLÁVKA and Tomáš VOJNAR. CRC64 Algorithm Analysis and Verification. Brno: CESNET, z. s. p. o., 2005. Technical Report 27/2005.
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KUČERA, Antonín and Richard MAYR. A Generic Framework for Checking Semantic Equivalences between Pushdown Automata and Finite-State Automata. In Exploring New Frontiers of Theoretical Informatics : IFIP 18th World Computer Congress, TC1 3rd International Conference on Theoretical Computer Science (TCS2004). Boston, Dordrecht, London: Kluwer, 2004. p. 395-408. ISBN 1-4020-8140-5.
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ANTOŠ, David, Vojtěch ŘEHÁK and Jan KOŘENEK. Hardware Router's Lookup Machine and its Formal Verification. In ICN'2004 Conference Proceedings. Gosier, Guadeloupe, French Caribbean: University of Haute Alsace, Colmar, France, 2004. p. 1002-1007. ISBN 0-86341-325-0.
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HOLEČEK, Jan, Tomáš KRATOCHVÍLA, Vojtěch ŘEHÁK, David ŠAFRÁNEK and Pavel ŠIMEČEK. How to Formalize FPGA Hardware Design. Praha: CESNET, z.s.p.o., 2004. CESNET Technical Report No. 04/2004.
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HOLEČEK, Jan, Tomáš KRATOCHVÍLA, Vojtěch ŘEHÁK, David ŠAFRÁNEK and Pavel ŠIMEČEK. Verification Process of Hardware Design in Liberouter Project. Praha: CESNET z.s.p.o., 2004. CESNET Technical Report No. 05/2004.
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HOLEČEK, Jan, Tomáš KRATOCHVÍLA, Vojtěch ŘEHÁK, David ŠAFRÁNEK and Pavel ŠIMEČEK. Verification Results in Liberouter Project. Praha: CESNET, z.s.p.o., 2004. CESNET Technical Report No. 03/2004.
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KRATOCHVÍLA, Tomáš, Vojtěch ŘEHÁK and Pavel ŠIMEČEK. Verification of COMBO6 VHDL Design. Praha: CESNET, z.s.p.o., 2003. CESNET Technical Report No. 17/2003.
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KUČERA, Antonín and Richard MAYR. INFINITY 2002. 4th International Workshop on Verification of Infinite-State Systems. 2002.
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CRHOVÁ, Jitka, Pavel KRČÁL, Jan STREJČEK, David ŠAFRÁNEK and Pavel ŠIMEČEK. YAHODA: verification tools database. In Proceedings of Tools Day. Brno: FI MU, 2002. p. 99-103.
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