Výpis publikací

2007

1. Verifying VHDL Designs with Multiple Clocks in SMV

   SMRČKA, Aleš, Vojtěch ŘEHÁK, Tomáš VOJNAR, David ŠAFRÁNEK, Petr MATOUŠEK a Zdeněk ŘEHÁK. Verifying VHDL Designs with Multiple Clocks in SMV. In Formal Methods Applications and Technology, 11th International Workshop on Formal Methods for Industrial Critical Systems, FMICS 2006, and 5th International Workshop on Parallel and Distributed Methods in Verification, PDMC 2006. Bonn: Springer-Verlag, 2007, s. 148-164, 16 s. ISBN 978-3-540-70951-0.

   Podrobněji: https://is.muni.cz/publication/639264/cs