FPGA implementation of MD5 hash algorithm is faster when
compared to software implementation, but brute-force attack on
MD5 still
needs 2^(128) iterations theoretically. This work will explore
the possibilities of improving the speed of brute-force attack
on FPGA implementation of MD5 algorithm. The student will
propose a design/method in FPGA to parallelize the search for a
password that was hashed with the MD5 algorithm. The student
will then implement the proposed design in an FPGA. As a proof
of concept the student will then
demonstrate the result for various password lengths suitable to
run
within reasonable amount of time, and compare performance with
the sequential implementation of brute-force attack in an FPGA
as
well as on a PC.