PA192 Secure hardware-based system design

Faculty of Informatics
Autumn 2015
Extent and Intensity
2/2/2. 6 credit(s) (plus extra credits for completion). Type of Completion: zk (examination).
prof. Ing. Václav Přenosil, CSc. (lecturer)
RNDr. Zdeněk Matěj, Ph.D. (lecturer)
Mgr. Filip Roth (lecturer)
RNDr. Martin Veškrna (seminar tutor)
RNDr. Filip Mravec, Ph.D. (seminar tutor)
Ahmad Abbadi, Ph.D. (seminar tutor)
Guaranteed by
prof. RNDr. Václav Matyáš, M.Sc., Ph.D.
Department of Computer Systems and Communications - Faculty of Informatics
Wed 16:00–17:50 A318
  • Timetable of Seminar Groups:
PA192/01: Mon 12:00–13:50 A415, A. Abbadi, Z. Matěj, F. Mravec, F. Roth, M. Veškrna
PA192/02: Mon 16:00–17:50 A415, A. Abbadi, Z. Matěj, F. Mravec, F. Roth, M. Veškrna
PA192/03: Mon 18:00–19:50 A415, A. Abbadi, Z. Matěj, F. Mravec, F. Roth, M. Veškrna
• Design of digital systems - encoding and data representation - logic algebra and optimization of the logical terms - implementation arithmetical and logical operations into digital systems - basic structural components of the digital systems - structure of the FPGA - theoretical tools for design of the combination circuits - theoretical tools for design of the sequential circuits - basic operational units of the digital systems - hazards of the digital systems • Architecture of digital systems - digital computer controllers and sequencers - operational memory addressing methods - operational and CACHE memory structure, operation principles - interruption system principles - direct memory access principles - input / output devices - power supply units, batteries, accumulators • Digital systems dependability - theory of reliability - hardware and software reliability of the digital systems - definition of the reliability, classification of the failures - simulation methods of the digital systems and reliability - fundamentals of theoretical and practical diagnostic - failures model of the technical systems - design methods of the combination and sequential logical circuits tests - hardware and software functionality checking tools of the digital system - hardware and software diagnostics tools of the digital systems - microprocessors systems testing and ROM BIOS
Course Enrolment Limitations
The course is offered to students of any study field.
Course objectives
The course is focused on architectures of secure digital systems, to ensure reliability, dependability and security of digital systems, assess and learn how to design safe and reliable digital systems. An important part of the course is to familiarize students with the principles and techniques of secure programming in language C and design of secure embedded systems. Course will present common problems and design of secure digital systems on real-world examples.
  • 1) Design of Digital Systems
  • i) design elements of digital systems
  • ii) design of the combinational circuits
  • iii) design of the sequential circuits
  • 2) Design of Digital Systems
  • i) digital systems cores
  • ii) design systems and simulation of the digital systems
  • 3) Architecture of Digital Systems
  • i) overview of microcontrollers, programmable arrays and DSP
  • ii) a/d and d/a converters
  • iii) digital signal processing methods
  • 4) Digital Systems Dependability
  • i) reliability evaluation of the electronics devices
  • ii) failures model of the technical systems
  • iii) methods and models of the redundancy
  • iv) Markov reliability and availability models
  • 5) Architecting Speed
  • i) High Throughput
  • ii) Low Latency
  • iii) Timing
  • 6) Rolling up the pipeline
  • opposite technique than this, when a high throughput was a target
  • 7) Controls to manage the reuse of logic
  • implementing a state machine to direct data flow in case of more complex variations to the input of a resource
  • 8) Sharing logic resources
  • different resources are shared across different functional boundaries. This type of resource sharing should be used whenever there are functional blocks that can be used in other areas of the design or even in different modules (counters).
  • 9) The impact of RESET
  • an improper reset strategy can create an unnecessarily large design or makes synthesis and optimization tools ineffective
  • i) Design without RESET capability
  • ii) Design without SET capability
  • iii) Design without asynchronous RESET capability
  • iv) Impact of RAM RESET
  • v) Optimization using set/reset pins for logic implementation.
  • 10) The most common errors (wrong design, incorrect use of the preprocessor, uncontrolled return values are ignored warning compiler, etc.)
  • Assert, errno
  • Event logging (syslog, multilevel listings)
  • 11) Debugging (kdbg, valgrind, process memory dump, etc.)
  • Access rights - a process file, use suid / sgid bit
  • Access control - locking (critical sections, files, memory)
  • 12) Work with temporary files
  • Processing of sensitive data (passwords, secure file deletion)
  • 13) User input processing (processing of command line parameters, data validation, buffer overflow)
  • 14) Protection of SW against reverse engineering
Teaching methods
The course consists of theoretical training, laboratory exercises and solutions independently will project. Topic of the project will be specified in the opening hour of laboratory exercises. It is possible to design your own project topic, which must be approved by the teacher.
Assessment methods
• laboratory tasks with the defense - 16 points
• mid-term test - 20 points
• evaluated project - 14 points
• final written exam - 50 points
• passing boundary for ECTS assessment - 50 points
Language of instruction
Further comments (probably available only in Czech)
Study Materials
The course is taught annually.
The course is also listed under the following terms Autumn 2013, Autumn 2014, Autumn 2016, Autumn 2017, Autumn 2018, Autumn 2019.
  • Enrolment Statistics (Autumn 2015, recent)
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