PV200 Introduction to hardware description languages
Faculty of InformaticsAutumn 2024
- Extent and Intensity
- 0/2/1. 3 credit(s) (plus extra credits for completion). Type of Completion: k (colloquium).
In-person direct teaching - Teacher(s)
- Ing. Jiří Čulen (lecturer)
prof. Ing. Václav Přenosil, CSc. (alternate examiner)
doc. RNDr. Zdeněk Matěj, Ph.D. (lecturer) - Guaranteed by
- doc. RNDr. Zdeněk Matěj, Ph.D.
Department of Computer Systems and Communications – Faculty of Informatics
Contact Person: doc. RNDr. Zdeněk Matěj, Ph.D.
Supplier department: Department of Computer Systems and Communications – Faculty of Informatics - Timetable of Seminar Groups
- PV200/01: Thu 26. 9. to Thu 19. 12. Thu 16:00–17:50 A415, J. Čulen, Z. Matěj
PV200/02: Thu 26. 9. to Thu 19. 12. Thu 18:00–19:50 A415, J. Čulen, Z. Matěj - Course Enrolment Limitations
- The course is also offered to the students of the fields other than those the course is directly associated with.
- fields of study / plans the course is directly associated with
- there are 32 fields of study the course is directly associated with, display
- Course objectives
- Within this course the students will obtain deeper knowledge on the field-programmable gate array (FPGA) and get familiar with advanced methods of hardware design using hardware description languages (HDL). Verilog HDL is used to demonstrate most of the principles.
- Learning outcomes
- Graduates of this course will be able to:
understand the FPGA principle;
design advanced systems using HDL Verilog version 2001
design application for FPGA. - Syllabus
- Programmable structures fundamentals.
- Structural modelling of programable logic using schematics, basics of simulations.
- Verilog HDL – concepts, basic syntax, structural modelling, design hierarchy.
- Behavioural modelling of combinational logic, decoders, adders, subtractors.
- Simulations by ModelSim, using of test benches
- Sequential logic - Counters, clock dividers
- Sequential logic – Synchronous design
- Sequential logic – Finite state machines
- Introduction to System Verilog and VHDL.
- Practical tasks in Quartus II suite.
- Literature
- Teaching methods
- Laboratory seminar.
- Assessment methods
- The evaluation consists of:
a) defense of a set of tasks submitted during semester
b) defense of final project. - Language of instruction
- English
- Follow-Up Courses
- Further comments (probably available only in Czech)
- Study Materials
The course is taught annually. - Teacher's information
- The course takes place in the EmLab - A415.
PV200 Introduction to hardware description languages
Faculty of InformaticsAutumn 2023
- Extent and Intensity
- 0/2/1. 3 credit(s) (plus extra credits for completion). Type of Completion: k (colloquium).
- Teacher(s)
- Ing. Jiří Čulen (lecturer)
prof. Ing. Václav Přenosil, CSc. (alternate examiner)
doc. RNDr. Zdeněk Matěj, Ph.D. (lecturer)
RNDr. Ondřej Herman (lecturer) - Guaranteed by
- doc. RNDr. Zdeněk Matěj, Ph.D.
Department of Computer Systems and Communications – Faculty of Informatics
Contact Person: doc. RNDr. Zdeněk Matěj, Ph.D.
Supplier department: Department of Computer Systems and Communications – Faculty of Informatics - Timetable of Seminar Groups
- PV200/01: Thu 16:00–17:50 A415, J. Čulen, Z. Matěj
PV200/02: Thu 18:00–19:50 A415, J. Čulen, Z. Matěj - Course Enrolment Limitations
- The course is also offered to the students of the fields other than those the course is directly associated with.
- fields of study / plans the course is directly associated with
- there are 72 fields of study the course is directly associated with, display
- Course objectives
- Within this course the students will obtain deeper knowledge on the field of programmable structures (e.g. FPGAs) and get familiar with advanced methods of hardware design using hardware description languages. Verilog HDL is used to demonstrate most of the principles.
- Learning outcomes
- Graduates of this course will be able to:
understand the FPGA principle;
understand the programming languages VHDL and Verilog;
design advanced systems using HDL languages;
program application for FPGA. - Syllabus
- Programmable structures fundamentals.
- Verilog HDL – concepts, basic syntax, abstraction levels, design hierarchy.
- Designing in Verilog – combinational primitives, sequential circuits, state machine design.
- FPGA devices – capabilities, limitations, programming. Advanced features in Verilog, best practice.
- Prefabricated components – IP cores, Megafunctions.
- Interfaces & Peripherals – RS232, LCD, keyboard.
- Introduction to VHDL.
- Softcore computing – introduction to soft-core processor system.
- Practical tasks in Quartus II suite.
- Literature
- 3. HDL - Chip Design, Douglas J. Smith, ISBN 0-9651934-3-8
- THOMAS, Donald E. and Philip R. MOORBY. The Verilog hardware description language. 5. ed. New York: Springer, 2002, xx, 381. ISBN 1402070896. info
- Teaching methods
- Laboratory seminar.
- Assessment methods
- The evaluation consists of:
a) defense of a set of tasks submitted during semester
b) defense of final project. - Language of instruction
- English
- Follow-Up Courses
- Further comments (probably available only in Czech)
- Study Materials
The course is taught annually. - Teacher's information
- The course takes place in the EmLab - A415.
PV200 Introduction to hardware description languages
Faculty of InformaticsAutumn 2022
- Extent and Intensity
- 0/2/1. 3 credit(s) (plus extra credits for completion). Type of Completion: k (colloquium).
- Teacher(s)
- Ing. Jiří Čulen (lecturer)
prof. Ing. Václav Přenosil, CSc. (alternate examiner)
doc. RNDr. Zdeněk Matěj, Ph.D. (lecturer)
RNDr. Ondřej Herman (lecturer) - Guaranteed by
- doc. RNDr. Zdeněk Matěj, Ph.D.
Department of Computer Systems and Communications – Faculty of Informatics
Contact Person: prof. Ing. Václav Přenosil, CSc.
Supplier department: Department of Computer Systems and Communications – Faculty of Informatics - Timetable of Seminar Groups
- PV200/01: Fri 8:00–9:50 A415, Z. Matěj
PV200/02: Fri 10:00–11:50 A415, Z. Matěj - Course Enrolment Limitations
- The course is also offered to the students of the fields other than those the course is directly associated with.
- fields of study / plans the course is directly associated with
- there are 72 fields of study the course is directly associated with, display
- Course objectives
- Within this course the students will obtain deeper knowledge on the field of programmable structures (e.g. FPGAs) and get familiar with advanced methods of hardware design using hardware description languages. Verilog HDL is used to demonstrate most of the principles.
- Learning outcomes
- Graduates of this course will be able to:
understand the FPGA principle;
understand the programming languages VHDL and Verilog;
design advanced systems using HDL languages;
program application for FPGA. - Syllabus
- Programmable structures fundamentals.
- Verilog HDL – concepts, basic syntax, abstraction levels, design hierarchy.
- Designing in Verilog – combinational primitives, sequential circuits, state machine design.
- FPGA devices – capabilities, limitations, programming. Advanced features in Verilog, best practice.
- Prefabricated components – IP cores, Megafunctions.
- Interfaces & Peripherals – RS232, LCD, keyboard.
- Introduction to VHDL.
- Softcore computing – introduction to soft-core processor system.
- Practical tasks in Quartus II suite.
- Literature
- 3. HDL - Chip Design, Douglas J. Smith, ISBN 0-9651934-3-8
- THOMAS, Donald E. and Philip R. MOORBY. The Verilog hardware description language. 5. ed. New York: Springer, 2002, xx, 381. ISBN 1402070896. info
- Teaching methods
- Laboratory seminar.
- Assessment methods
- The evaluation consists of:
a) defense of a set of tasks submitted during semester
b) defense of final project. - Language of instruction
- English
- Follow-Up Courses
- Further comments (probably available only in Czech)
- The course is taught annually.
- Teacher's information
- The course takes place in the EmLab - A415.
PV200 Introduction to hardware description languages
Faculty of InformaticsAutumn 2021
- Extent and Intensity
- 0/2/1. 3 credit(s) (plus extra credits for completion). Type of Completion: k (colloquium).
- Teacher(s)
- Ing. Jiří Čulen (lecturer)
prof. Ing. Václav Přenosil, CSc. (alternate examiner)
doc. RNDr. Zdeněk Matěj, Ph.D. (lecturer)
RNDr. Ondřej Herman (lecturer) - Guaranteed by
- doc. RNDr. Zdeněk Matěj, Ph.D.
Department of Computer Systems and Communications – Faculty of Informatics
Contact Person: prof. Ing. Václav Přenosil, CSc.
Supplier department: Department of Computer Systems and Communications – Faculty of Informatics - Timetable of Seminar Groups
- PV200/01: Fri 17. 9. to Fri 10. 12. Fri 10:00–11:50 A415, J. Čulen, Z. Matěj
PV200/02: Fri 17. 9. to Fri 10. 12. Fri 8:00–9:50 A415, J. Čulen, Z. Matěj - Course Enrolment Limitations
- The course is also offered to the students of the fields other than those the course is directly associated with.
- fields of study / plans the course is directly associated with
- there are 71 fields of study the course is directly associated with, display
- Course objectives
- Within this course the students will obtain deeper knowledge on the field of programmable structures (e.g. FPGAs) and get familiar with advanced methods of hardware design using hardware description languages. Verilog HDL is used to demonstrate most of the principles.
- Learning outcomes
- Graduates of this course will be able to:
understand the FPGA principle;
understand the programming languages VHDL and Verilog;
design advanced systems using HDL languages;
program application for FPGA. - Syllabus
- Programmable structures fundamentals.
- Verilog HDL – concepts, basic syntax, abstraction levels, design hierarchy.
- Designing in Verilog – combinational primitives, sequential circuits, state machine design.
- FPGA devices – capabilities, limitations, programming. Advanced features in Verilog, best practice.
- Prefabricated components – IP cores, Megafunctions.
- Interfaces & Peripherals – RS232, LCD, keyboard.
- Introduction to VHDL.
- Softcore computing – introduction to soft-core processor system.
- Practical tasks in Quartus II suite.
- Literature
- 3. HDL - Chip Design, Douglas J. Smith, ISBN 0-9651934-3-8
- THOMAS, Donald E. and Philip R. MOORBY. The Verilog hardware description language. 5. ed. New York: Springer, 2002, xx, 381. ISBN 1402070896. info
- Teaching methods
- Laboratory seminar.
- Assessment methods
- The evaluation consists of:
a) defense of a set of tasks submitted during semester
b) defense of final project. - Language of instruction
- English
- Follow-Up Courses
- Further comments (probably available only in Czech)
- The course is taught annually.
- Teacher's information
- The course takes place in the EmLab - A415.
PV200 Introduction to hardware description languages
Faculty of InformaticsAutumn 2020
- Extent and Intensity
- 0/2/1. 3 credit(s) (plus extra credits for completion). Type of Completion: k (colloquium).
- Teacher(s)
- RNDr. Ondřej Herman (lecturer)
prof. Ing. Václav Přenosil, CSc. (alternate examiner)
doc. RNDr. Zdeněk Matěj, Ph.D. (lecturer) - Guaranteed by
- doc. RNDr. Zdeněk Matěj, Ph.D.
Department of Computer Systems and Communications – Faculty of Informatics
Contact Person: prof. Ing. Václav Přenosil, CSc.
Supplier department: Department of Computer Systems and Communications – Faculty of Informatics - Timetable of Seminar Groups
- PV200/01: Fri 10:00–11:50 A415, O. Herman, Z. Matěj
PV200/02: Tue 16:00–17:50 A415, O. Herman, Z. Matěj - Course Enrolment Limitations
- The course is also offered to the students of the fields other than those the course is directly associated with.
- fields of study / plans the course is directly associated with
- there are 71 fields of study the course is directly associated with, display
- Course objectives
- Within this course the students will obtain deeper knowledge on the field of programmable structures (e.g. FPGAs) and get familiar with advanced methods of hardware design using hardware description languages. Verilog HDL is used to demonstrate most of the principles.
- Learning outcomes
- Graduates of this course will be able to:
understand the FPGA principle;
understand the programming languages VHDL and Verilog;
design advanced systems using HDL languages;
program application for FPGA. - Syllabus
- Programmable structures fundamentals.
- Verilog HDL – concepts, basic syntax, abstraction levels, design hierarchy.
- Designing in Verilog – combinational primitives, sequential circuits, state machine design.
- FPGA devices – capabilities, limitations, programming. Advanced features in Verilog, best practice.
- Prefabricated components – IP cores, Megafunctions.
- Interfaces & Peripherals – RS232, LCD, keyboard.
- Introduction to VHDL.
- Softcore computing – introduction to soft-core processor system.
- Practical tasks in Quartus II suite.
- Literature
- 3. HDL - Chip Design, Douglas J. Smith, ISBN 0-9651934-3-8
- THOMAS, Donald E. and Philip R. MOORBY. The Verilog hardware description language. 5. ed. New York: Springer, 2002, xx, 381. ISBN 1402070896. info
- Teaching methods
- Laboratory seminar.
- Assessment methods
- The evaluation consists of:
a) defense of a set of tasks submitted during semester
b) defense of final project. - Language of instruction
- English
- Follow-Up Courses
- Further comments (probably available only in Czech)
- The course is taught annually.
- Teacher's information
- The course takes place in the EmLab - A415.
PV200 Introduction to hardware description languages
Faculty of InformaticsAutumn 2019
- Extent and Intensity
- 0/2/1. 3 credit(s) (plus extra credits for completion). Type of Completion: k (colloquium).
- Teacher(s)
- RNDr. Ondřej Herman (lecturer)
prof. Ing. Václav Přenosil, CSc. (alternate examiner)
doc. RNDr. Zdeněk Matěj, Ph.D. (lecturer) - Guaranteed by
- doc. RNDr. Zdeněk Matěj, Ph.D.
Department of Computer Systems and Communications – Faculty of Informatics
Contact Person: prof. Ing. Václav Přenosil, CSc.
Supplier department: Department of Computer Systems and Communications – Faculty of Informatics - Timetable of Seminar Groups
- PV200/01: Mon 14:00–15:50 A415, O. Herman, Z. Matěj
PV200/02: Thu 10:00–11:50 A415, O. Herman, Z. Matěj - Course Enrolment Limitations
- The course is also offered to the students of the fields other than those the course is directly associated with.
- fields of study / plans the course is directly associated with
- there are 71 fields of study the course is directly associated with, display
- Course objectives
- Within this course the students will obtain deeper knowledge on the field of programmable structures (e.g. FPGAs) and get familiar with advanced methods of hardware design using hardware description languages. Verilog HDL is used to demonstrate most of the principles.
- Learning outcomes
- Graduates of this course will be able to: understand the FPGA principle understand the programming languages VHDL and Verilog design advanced systems using HDL languages program application for FPGA
- Syllabus
- Programmable structures fundamentals.
- Verilog HDL – concepts, basic syntax, abstraction levels, design hierarchy.
- Designing in Verilog – combinational primitives, sequential circuits, state machine design.
- FPGA devices – capabilities, limitations, programming. Advanced features in Verilog, best practice.
- Prefabricated components – IP cores, Megafunctions.
- Interfaces & Peripherals – RS232, LCD, keyboard.
- Introduction to VHDL.
- Sofcore computing – introduction to NIOS2 processor system.
- Practical tasks in Quartus II suite.
- Literature
- 3. HDL - Chip Design, Douglas J. Smith, ISBN 0-9651934-3-8
- THOMAS, Donald E. and Philip R. MOORBY. The Verilog hardware description language. 5. ed. New York: Springer, 2002, xx, 381. ISBN 1402070896. info
- Teaching methods
- Laboratory seminar.
- Assessment methods
- Evaluation consists of: a) defense of set of tasks submitted during semester b) defense of final project.
- Language of instruction
- English
- Follow-Up Courses
- Further comments (probably available only in Czech)
- Study Materials
The course is taught annually. - Teacher's information
- http://l202.fi.muni.cz/vyuka/pv200/start
PV200 Introduction to hardware description languages
Faculty of InformaticsAutumn 2018
- Extent and Intensity
- 0/2/1. 3 credit(s) (plus extra credits for completion). Type of Completion: k (colloquium).
- Teacher(s)
- doc. RNDr. Zdeněk Matěj, Ph.D. (lecturer)
prof. Ing. Václav Přenosil, CSc. (alternate examiner)
Bc. Dominik Salvet (lecturer) - Guaranteed by
- doc. RNDr. Aleš Horák, Ph.D.
Department of Machine Learning and Data Processing – Faculty of Informatics
Contact Person: prof. Ing. Václav Přenosil, CSc.
Supplier department: Department of Machine Learning and Data Processing – Faculty of Informatics - Timetable
- Fri 10:00–11:50 A415
- Prerequisites
- Study of PV200 course does not require preliminary knowledge.
- Course Enrolment Limitations
- The course is also offered to the students of the fields other than those the course is directly associated with.
- fields of study / plans the course is directly associated with
- there are 39 fields of study the course is directly associated with, display
- Course objectives
- Within this course the students will obtain deeper knowledge on the field of programmable structures (e.g. FPGAs) and get familiar with advanced methods of hardware design using hardware description languages. Verilog HDL is used to demonstrate most of the principles.
- Learning outcomes
- Graduates of this course will be able to: - understand the FPGA principle; - understand the programming languages VHDL and Verilog; - design advanced systems using HDL languages; - program application for FPGA.
- Syllabus
- - programmable structures fundamentals;
- - Verilog HDL – concepts, basic syntax, abstraction levels, design hierarchy;
- - designing in Verilog – combinational primitives, sequential circuits, state machine design;
- - FPGA devices – capabilities, limitations, programming. Advanced features in Verilog, best practice;
- - prefabricated components – IP cores, Megafunctions;
- - interfaces & Peripherals – RS232, LCD, keyboard;
- - introduction to VHDL;
- - sofcore computing – introduction to NIOS2 processor system;
- - practical tasks in Quartus II suite.
- Literature
- 3. HDL - Chip Design, Douglas J. Smith, ISBN 0-9651934-3-8
- THOMAS, Donald E. and Philip R. MOORBY. The Verilog hardware description language. 5. ed. New York: Springer, 2002, xx, 381. ISBN 1402070896. info
- Teaching methods
- Laboratory seminar.
- Assessment methods
- Evaluation consists of:
a) defense of set of tasks submitted during semester;
b) defense of final project. - Language of instruction
- English
- Follow-Up Courses
- Further comments (probably available only in Czech)
- Study Materials
The course is taught annually. - Teacher's information
- http://l202.fi.muni.cz/vyuka/pv200/start
PV200 Introduction to hardware description languages
Faculty of InformaticsAutumn 2017
- Extent and Intensity
- 0/2/1. 3 credit(s) (plus extra credits for completion). Type of Completion: k (colloquium).
- Teacher(s)
- doc. RNDr. Zdeněk Matěj, Ph.D. (lecturer)
Mgr. Filip Roth (seminar tutor)
prof. Ing. Václav Přenosil, CSc. (alternate examiner)
Mgr. Martin Pavelek (seminar tutor) - Guaranteed by
- doc. RNDr. Aleš Horák, Ph.D.
Department of Machine Learning and Data Processing – Faculty of Informatics
Contact Person: prof. Ing. Václav Přenosil, CSc.
Supplier department: Department of Machine Learning and Data Processing – Faculty of Informatics - Timetable
- Mon 16:00–17:50 A415
- Prerequisites
- Study of PV200 course does not require preliminary knowledge.
- Course Enrolment Limitations
- The course is also offered to the students of the fields other than those the course is directly associated with.
- fields of study / plans the course is directly associated with
- there are 39 fields of study the course is directly associated with, display
- Course objectives
- Within this course the students will obtain deeper knowledge on the field of programmable structures (e.g. FPGAs) and get familiar with advanced methods of hardware design using hardware description languages. Verilog HDL is used to demonstrate most of the principles.
- Learning outcomes
- Graduates of this course will be able to: - understand the FPGA principle; - understand the programming languages VHDL and Verilog; - design advanced systems using HDL languages; - program application for FPGA.
- Syllabus
- - programmable structures fundamentals;
- - Verilog HDL – concepts, basic syntax, abstraction levels, design hierarchy;
- - designing in Verilog – combinational primitives, sequential circuits, state machine design;
- - FPGA devices – capabilities, limitations, programming. Advanced features in Verilog, best practice;
- - prefabricated components – IP cores, Megafunctions;
- - interfaces & Peripherals – RS232, LCD, keyboard;
- - introduction to VHDL;
- - sofcore computing – introduction to NIOS2 processor system;
- - practical tasks in Quartus II suite.
- Literature
- 3. HDL - Chip Design, Douglas J. Smith, ISBN 0-9651934-3-8
- THOMAS, Donald E. and Philip R. MOORBY. The Verilog hardware description language. 5. ed. New York: Springer, 2002, xx, 381. ISBN 1402070896. info
- Teaching methods
- Laboratory seminar.
- Assessment methods
- Evaluation consists of:
a) defense of set of tasks submitted during semester;
b) defense of final project. - Language of instruction
- English
- Follow-Up Courses
- Further comments (probably available only in Czech)
- Study Materials
The course is taught annually. - Teacher's information
- http://l202.fi.muni.cz/vyuka/pv200/start
PV200 Introduction to hardware description languages
Faculty of InformaticsAutumn 2016
- Extent and Intensity
- 0/2/1. 3 credit(s) (plus extra credits for completion). Type of Completion: k (colloquium).
- Teacher(s)
- doc. RNDr. Zdeněk Matěj, Ph.D. (lecturer)
Mgr. Filip Roth (seminar tutor)
prof. Ing. Václav Přenosil, CSc. (alternate examiner)
RNDr. Martin Veškrna (lecturer)
RNDr. Filip Mravec, Ph.D. (lecturer)
Ahmad Abbadi, Ph.D. (lecturer) - Guaranteed by
- doc. RNDr. Aleš Horák, Ph.D.
Department of Machine Learning and Data Processing – Faculty of Informatics
Contact Person: prof. Ing. Václav Přenosil, CSc.
Supplier department: Department of Machine Learning and Data Processing – Faculty of Informatics - Timetable
- Mon 8:00–9:50 A415
- Prerequisites
- Knowledge on the level of PV170 Design of Digital Systems and PV172 Digital Systems Architecture.
- Course Enrolment Limitations
- The course is also offered to the students of the fields other than those the course is directly associated with.
- fields of study / plans the course is directly associated with
- there are 39 fields of study the course is directly associated with, display
- Course objectives
- Within this course the students will obtain deeper knowledge on the field of programmable structures (e.g. FPGAs) and get familiar with advanced methods of hardware design using hardware description languages. Verilog HDL is used to demonstrate most of the principles.
- Syllabus
- Programmable structures fundamentals.
- Verilog HDL – concepts, basic syntax, abstraction levels, design hierarchy.
- Designing in Verilog – combinational primitives, sequential circuits, state machine design.
- FPGA devices – capabilities, limitations, programming. Advanced features in Verilog, best practice.
- Prefabricated components – IP cores, Megafunctions.
- Interfaces & Peripherals – RS232, LCD, keyboard.
- Introduction to VHDL.
- Sofcore computing – introduction to NIOS2 processor system.
- Practical tasks in Quartus II suite.
- Literature
- 3. HDL - Chip Design, Douglas J. Smith, ISBN 0-9651934-3-8
- THOMAS, Donald E. and Philip R. MOORBY. The Verilog hardware description language. 5. ed. New York: Springer, 2002, xx, 381. ISBN 1402070896. info
- Teaching methods
- Laboratory seminar.
- Assessment methods
- Evaluation consists of: a) defense of set of tasks submitted during semester b) defense of final project.
- Language of instruction
- English
- Follow-Up Courses
- Further comments (probably available only in Czech)
- The course is taught annually.
- Teacher's information
- http://l202.fi.muni.cz/vyuka/pv200/start
PV200 Introduction to hardware description languages
Faculty of InformaticsAutumn 2015
- Extent and Intensity
- 0/2/1. 3 credit(s) (plus extra credits for completion). Type of Completion: k (colloquium).
- Teacher(s)
- doc. RNDr. Zdeněk Matěj, Ph.D. (lecturer)
Mgr. Filip Roth (seminar tutor)
prof. Ing. Václav Přenosil, CSc. (alternate examiner)
RNDr. Martin Veškrna (lecturer)
RNDr. Filip Mravec, Ph.D. (lecturer)
Ahmad Abbadi, Ph.D. (lecturer) - Guaranteed by
- doc. RNDr. Aleš Horák, Ph.D.
Department of Machine Learning and Data Processing – Faculty of Informatics
Contact Person: prof. Ing. Václav Přenosil, CSc.
Supplier department: Department of Machine Learning and Data Processing – Faculty of Informatics - Timetable
- Wed 16:00–17:50 A415
- Prerequisites
- Knowledge on the level of PV170 Design of Digital Systems and PV172 Digital Systems Architecture.
- Course Enrolment Limitations
- The course is also offered to the students of the fields other than those the course is directly associated with.
- fields of study / plans the course is directly associated with
- there are 39 fields of study the course is directly associated with, display
- Course objectives
- Within this course the students will obtain deeper knowledge on the field of programmable structures (e.g. FPGAs) and get familiar with advanced methods of hardware design using hardware description languages. Verilog HDL is used to demonstrate most of the principles.
- Syllabus
- Programmable structures fundamentals.
- Verilog HDL – concepts, basic syntax, abstraction levels, design hierarchy.
- Designing in Verilog – combinational primitives, sequential circuits, state machine design.
- FPGA devices – capabilities, limitations, programming. Advanced features in Verilog, best practice.
- Prefabricated components – IP cores, Megafunctions.
- Interfaces & Peripherals – RS232, LCD, keyboard.
- Introduction to VHDL.
- Sofcore computing – introduction to NIOS2 processor system.
- Practical tasks in Quartus II suite.
- Literature
- 3. HDL - Chip Design, Douglas J. Smith, ISBN 0-9651934-3-8
- THOMAS, Donald E. and Philip R. MOORBY. The Verilog hardware description language. 5. ed. New York: Springer, 2002, xx, 381. ISBN 1402070896. info
- Teaching methods
- Laboratory seminar.
- Assessment methods
- Evaluation consists of: a) defense of set of tasks submitted during semester b) defense of final project.
- Language of instruction
- English
- Follow-Up Courses
- Further comments (probably available only in Czech)
- Study Materials
The course is taught annually. - Teacher's information
- http://l202.fi.muni.cz/vyuka/pv200/start
PV200 Introduction to hardware description languages
Faculty of InformaticsAutumn 2014
- Extent and Intensity
- 0/2/1. 3 credit(s) (plus extra credits for completion). Type of Completion: k (colloquium).
- Teacher(s)
- RNDr. Martin Veškrna (lecturer)
Mgr. Martin Elich (assistant)
prof. Ing. Václav Přenosil, CSc. (alternate examiner)
RNDr. Filip Mravec, Ph.D. (lecturer)
Mgr. Šimon Řeřucha, Ph.D. (lecturer) - Guaranteed by
- prof. Ing. Václav Přenosil, CSc.
Department of Machine Learning and Data Processing – Faculty of Informatics
Contact Person: prof. Ing. Václav Přenosil, CSc.
Supplier department: Department of Machine Learning and Data Processing – Faculty of Informatics - Timetable
- Wed 10:00–11:50 A415
- Prerequisites
- Knowledge on the level of PV170 Design of Digital Systems and PV172 Digital Systems Architecture.
- Course Enrolment Limitations
- The course is also offered to the students of the fields other than those the course is directly associated with.
- fields of study / plans the course is directly associated with
- there are 38 fields of study the course is directly associated with, display
- Course objectives
- Within this course the students will obtain deeper knowledge on the field of programmable structures (e.g. FPGAs) and get familiar with advanced methods of hardware design using hardware description languages. Verilog HDL is used to demonstrate most of the principles.
- Syllabus
- Programmable structures fundamentals.
- Verilog HDL – concepts, basic syntax, abstraction levels, design hierarchy.
- Designing in Verilog – combinational primitives, sequential circuits, state machine design.
- FPGA devices – capabilities, limitations, programming. Advanced features in Verilog, best practice.
- Prefabricated components – IP cores, Megafunctions.
- Interfaces & Peripherals – RS232, LCD, keyboard.
- Introduction to VHDL.
- Sofcore computing – introduction to NIOS2 processor system.
- Practical tasks in Quartus II suite.
- Literature
- 3. HDL - Chip Design, Douglas J. Smith, ISBN 0-9651934-3-8
- THOMAS, Donald E. and Philip R. MOORBY. The Verilog hardware description language. 5. ed. New York: Springer, 2002, xx, 381. ISBN 1402070896. info
- Teaching methods
- Laboratory seminar.
- Assessment methods
- Evaluation consists of: a) defense of set of tasks submitted during semester b) defense of final project.
- Language of instruction
- English
- Follow-Up Courses
- Further comments (probably available only in Czech)
- Study Materials
The course is taught annually. - Teacher's information
- http://l202.fi.muni.cz/vyuka/pv200/start
PV200 Introduction to hardware description languages
Faculty of InformaticsAutumn 2013
- Extent and Intensity
- 0/2/1. 3 credit(s) (plus extra credits for completion). Type of Completion: k (colloquium).
- Teacher(s)
- doc. RNDr. Zdeněk Matěj, Ph.D. (lecturer)
Mgr. Martin Elich (assistant)
prof. Ing. Václav Přenosil, CSc. (alternate examiner)
Mgr. Šimon Řeřucha, Ph.D. (lecturer) - Guaranteed by
- prof. Ing. Václav Přenosil, CSc.
Department of Machine Learning and Data Processing – Faculty of Informatics
Contact Person: prof. Ing. Václav Přenosil, CSc.
Supplier department: Department of Machine Learning and Data Processing – Faculty of Informatics - Timetable of Seminar Groups
- PV200/01: Mon 10:00–11:50 B202, Z. Matěj, Š. Řeřucha
- Prerequisites
- Knowledge on the level of PV170 Design of Digital Systems and PV172 Digital Systems Architecture.
- Course Enrolment Limitations
- The course is also offered to the students of the fields other than those the course is directly associated with.
- fields of study / plans the course is directly associated with
- there are 38 fields of study the course is directly associated with, display
- Course objectives
- Within this course the students will obtain deeper knowledge on the field of programmable structures (e.g. FPGAs) and get familiar with advanced methods of hardware design using hardware description languages. Verilog HDL is used to demonstrate most of the principles.
- Syllabus
- Programmable structures fundamentals.
- Verilog HDL – concepts, basic syntax, abstraction levels, design hierarchy.
- Designing in Verilog – combinational primitives, sequential circuits, state machine design.
- FPGA devices – capabilities, limitations, programming. Advanced features in Verilog, best practice.
- Prefabricated components – IP cores, Megafunctions.
- Interfaces & Peripherals – RS232, LCD, keyboard.
- Introduction to VHDL.
- Sofcore computing – introduction to NIOS2 processor system.
- Practical tasks in Quartus II suite.
- Literature
- 3. HDL - Chip Design, Douglas J. Smith, ISBN 0-9651934-3-8
- THOMAS, Donald E. and Philip R. MOORBY. The Verilog hardware description language. 5. ed. New York: Springer, 2002, xx, 381. ISBN 1402070896. info
- Teaching methods
- Laboratory seminar.
- Assessment methods
- Evaluation consists of: a) defense of set of tasks submitted during semester b) defense of final project.
- Language of instruction
- English
- Follow-Up Courses
- Further comments (probably available only in Czech)
- Study Materials
The course is taught annually. - Teacher's information
- http://l202.fi.muni.cz/vyuka/pv200/start
PV200 Introduction to hardware description languages
Faculty of InformaticsAutumn 2012
- Extent and Intensity
- 0/2/1. 3 credit(s) (plus extra credits for completion). Type of Completion: k (colloquium).
- Teacher(s)
- Ing. Petr Bojda, Ph.D. (lecturer), prof. Ing. Václav Přenosil, CSc. (deputy)
prof. Ing. Václav Přenosil, CSc. (alternate examiner)
Mgr. Martin Elich (lecturer)
RNDr. Radek Krejčí (lecturer) - Guaranteed by
- prof. Ing. Václav Přenosil, CSc.
Department of Machine Learning and Data Processing – Faculty of Informatics
Contact Person: prof. Ing. Václav Přenosil, CSc.
Supplier department: Department of Machine Learning and Data Processing – Faculty of Informatics - Timetable of Seminar Groups
- PV200/PV200a: Tue 14:00–15:50 B202, P. Bojda, M. Elich, R. Krejčí, V. Přenosil
PV200/PV200b: Tue 16:00–17:50 B202, P. Bojda, M. Elich, R. Krejčí, V. Přenosil - Prerequisites
- Knowledge on the level of PV170 Design of Digital Systems and PV172 Digital Computer Architecture.
- Course Enrolment Limitations
- The course is also offered to the students of the fields other than those the course is directly associated with.
- fields of study / plans the course is directly associated with
- there are 38 fields of study the course is directly associated with, display
- Course objectives
- Within this course the students will obtain deeper knowledge on the field of programmable structures (e.g. FPGAs) and get familiar with advanced methods of hardware design using hardware description languages. Verilog HDL is used to demonstrate most of the principles.
- Syllabus
- Programmable structures fundamentals.
- Verilog HDL – concepts, basic syntax, abstraction levels, design hierarchy.
- Designing in Verilog – combinational primitives, sequential circuits, state machine design.
- FPGA devices – capabilities, limitations, programming. Advanced features in Verilog, best practice.
- Prefabricated components – IP cores, Megafunctions.
- Interfaces & Peripherals – RS232, LCD, keyboard.
- Introduction to VHDL.
- Sofcore computing – introduction to NIOS2 processor system.
- Practical tasks in Quartus II suite.
- Literature
- 3. HDL - Chip Design, Douglas J. Smith, ISBN 0-9651934-3-8
- THOMAS, Donald E. and Philip R. MOORBY. The Verilog hardware description language. 5. ed. New York: Springer, 2002, xx, 381. ISBN 1402070896. info
- Teaching methods
- Laboratory seminar.
- Assessment methods
- Evaluation consists of: a) defence of set of tasks submitted during semester b) defence of final project.
- Language of instruction
- English
- Follow-Up Courses
- Further comments (probably available only in Czech)
- Study Materials
The course is taught annually. - Teacher's information
- http://l202.fi.muni.cz/vyuka/pv200/start
PV200 Introduction to hardware description languages
Faculty of InformaticsAutumn 2011
- Extent and Intensity
- 0/2/1. 3 credit(s) (plus extra credits for completion). Type of Completion: k (colloquium).
- Teacher(s)
- doc. RNDr. Zdeněk Matěj, Ph.D. (lecturer)
RNDr. Radek Krejčí (assistant)
Mgr. Martin Elich (lecturer) - Guaranteed by
- prof. Ing. Václav Přenosil, CSc.
Department of Machine Learning and Data Processing – Faculty of Informatics
Contact Person: prof. Ing. Václav Přenosil, CSc. - Timetable
- Thu 13:00–14:50 B202
- Prerequisites
- Knowledge on the level of PV170 Design of Digital Systems and PV172 Digital Computer Architecture.
- Course Enrolment Limitations
- The course is also offered to the students of the fields other than those the course is directly associated with.
- fields of study / plans the course is directly associated with
- there are 38 fields of study the course is directly associated with, display
- Course objectives
- Within this course the students will obtain deeper knowledge on the field of programmable structures (e.g. FPGAs) and get familiar with advanced methods of hardware design using hardware description languages. Verilog HDL is used to demonstrate most of the principles.
- Syllabus
- Programmable structures fundamentals.
- Verilog HDL – concepts, basic syntax, abstraction levels, design hierarchy.
- Designing in Verilog – combinational primitives, sequential circuits, state machine design.
- FPGA devices – capabilities, limitations, programming. Advanced features in Verilog, best practice.
- Prefabricated components – IP cores, Megafunctions.
- Interfaces & Peripherals – RS232, LCD, keyboard.
- Introduction to VHDL.
- Sofcore computing – introduction to NIOS2 processor system.
- Practical tasks in Quartus II suite.
- Literature
- 3. HDL - Chip Design, Douglas J. Smith, ISBN 0-9651934-3-8
- THOMAS, Donald E. and Philip R. MOORBY. The Verilog hardware description language. 5. ed. New York: Springer, 2002, xx, 381. ISBN 1402070896. info
- Teaching methods
- Laboratory seminar.
- Assessment methods
- Evaluation consists of: a) defence of set of tasks submitted during semester b) defence of final project.
- Language of instruction
- English
- Follow-Up Courses
- Further comments (probably available only in Czech)
- Study Materials
The course is taught annually. - Teacher's information
- http://l202.fi.muni.cz/vyuka/pv200/start
PV200 Introduction to hardware description languages
Faculty of InformaticsAutumn 2010
- Extent and Intensity
- 0/2/1. 3 credit(s) (plus extra credits for completion). Type of Completion: k (colloquium).
- Teacher(s)
- Mgr. Šimon Řeřucha, Ph.D. (lecturer)
RNDr. Radek Krejčí (assistant)
doc. RNDr. Zdeněk Matěj, Ph.D. (lecturer) - Guaranteed by
- prof. Ing. Václav Přenosil, CSc.
Department of Machine Learning and Data Processing – Faculty of Informatics
Contact Person: prof. Ing. Václav Přenosil, CSc. - Timetable
- Thu 14:00–17:50 B202
- Prerequisites
- Knowledge on the level of PV170 Design of Digital Systems and PV172 Digital Computer Architecture.
- Course Enrolment Limitations
- The course is also offered to the students of the fields other than those the course is directly associated with.
- fields of study / plans the course is directly associated with
- there are 42 fields of study the course is directly associated with, display
- Course objectives
- Within this course the students will obtain deeper knowledge on the field of programmable structures (e.g. FPGAs) and get familiar with advanced methods of hardware design using hardware description languages. Verilog HDL is used to demonstrate most of the principles.
- Syllabus
- Programmable structures fundamentals.
- Verilog HDL – concepts, basic syntax, abstraction levels, design hierarchy.
- Designing in Verilog – combinational primitives, sequential circuits, state machine design.
- FPGA devices – capabilities, limitations, programming. Advanced features in Verilog, best practice.
- Prefabricated components – IP cores, Megafunctions.
- Interfaces & Peripherals – RS232, LCD, keyboard.
- Introduction to VHDL.
- Sofcore computing – introduction to NIOS2 processor system.
- Practical tasks in Quartus II suite.
- Literature
- 3. HDL - Chip Design, Douglas J. Smith, ISBN 0-9651934-3-8
- THOMAS, Donald E. and Philip R. MOORBY. The Verilog hardware description language. 5. ed. New York: Springer, 2002, xx, 381. ISBN 1402070896. info
- Teaching methods
- Laboratory seminar.
- Assessment methods
- Evaluation consists of: a) defence of set of tasks submitted during semester b) defence of final project.
- Language of instruction
- English
- Follow-Up Courses
- Further comments (probably available only in Czech)
- Study Materials
The course is taught annually. - Teacher's information
- http://l202.fi.muni.cz/vyuka/pv200/start
PV200 Introduction to hardware description languages
Faculty of InformaticsAutumn 2009
- Extent and Intensity
- 0/2/1. 3 credit(s) (plus extra credits for completion). Type of Completion: k (colloquium).
- Teacher(s)
- Mgr. Šimon Řeřucha, Ph.D. (lecturer)
doc. Mgr. Radek Pelánek, Ph.D. (lecturer)
doc. RNDr. Zdeněk Matěj, Ph.D. (lecturer)
RNDr. Vojtěch Krmíček, Ph.D. (assistant) - Guaranteed by
- prof. Ing. Václav Přenosil, CSc.
Department of Machine Learning and Data Processing – Faculty of Informatics
Contact Person: prof. Ing. Václav Přenosil, CSc. - Timetable
- Thu 10:00–11:50 B202
- Prerequisites
- Knowledge on the level of PV170 Design of Digital Systems and PV172 Digital Computer Architecture.
- Course Enrolment Limitations
- The course is also offered to the students of the fields other than those the course is directly associated with.
- fields of study / plans the course is directly associated with
- there are 40 fields of study the course is directly associated with, display
- Course objectives
- Within this course the students will obtain deeper knowledge on the field of programmable structures (e.g. FPGAs) and get familiar with advanced methods of hardware design using hardware description languages. Verilog HDL is used to demonstrate most of the principles.
- Syllabus
- Programmable structures fundamentals.
- Verilog HDL – concepts, basic syntax, abstraction levels, design hierarchy.
- Designing in Verilog – combinational primitives, sequential circuits, state machine design.
- FPGA devices – capabilities, limitations, programming. Advanced features in Verilog, best practice.
- Prefabricated components – IP cores, Megafunctions.
- Interfaces & Peripherals – RS232, LCD, keyboard.
- Introduction to VHDL.
- Sofcore computing – introduction to NIOS2 processor system.
- Practical tasks in Quartus II suite.
- Literature
- 3. HDL - Chip Design, Douglas J. Smith, ISBN 0-9651934-3-8
- THOMAS, Donald E. and Philip R. MOORBY. The Verilog hardware description language. 5. ed. New York: Springer, 2002, xx, 381. ISBN 1402070896. info
- Teaching methods
- Laboratory seminar.
- Assessment methods
- Evaluation consists of: a) defence of set of tasks submitted during semester b) defence of final project.
- Language of instruction
- English
- Follow-Up Courses
- Further comments (probably available only in Czech)
- The course is taught annually.
- Teacher's information
- http://l202.fi.muni.cz/vyuka/pv200/start
PV200 Programable Structures
Faculty of InformaticsAutumn 2008
- Extent and Intensity
- 0/2/1. 3 credit(s) (plus extra credits for completion). Recommended Type of Completion: k (colloquium). Other types of completion: zk (examination), z (credit).
- Teacher(s)
- doc. Mgr. Radek Pelánek, Ph.D. (lecturer)
RNDr. Vojtěch Krmíček, Ph.D. (assistant)
Mgr. Šimon Řeřucha, Ph.D. (lecturer)
Ing. Zbyněk Bureš, Ph.D. (assistant) - Guaranteed by
- prof. Ing. Václav Přenosil, CSc.
Department of Machine Learning and Data Processing – Faculty of Informatics
Contact Person: prof. Ing. Václav Přenosil, CSc. - Timetable
- Tue 10:00–11:50 B202, Tue 12:00–13:50 B202
- Prerequisites
- Knowledge on the level of PV170 Design of the computer machines and PV172 Digital Computer Architecture.
- Course Enrolment Limitations
- The course is also offered to the students of the fields other than those the course is directly associated with.
The capacity limit for the course is 20 student(s).
Current registration and enrolment status: enrolled: 0/20, only registered: 0/20, only registered with preference (fields directly associated with the programme): 0/20 - fields of study / plans the course is directly associated with
- there are 33 fields of study the course is directly associated with, display
- Course objectives
- Course is directed to assumption of the application virtuosity for following activities:
programming of the programmable structures;
control of the design tools;
application of the design methods for programmable structures implementation. - Syllabus
- Operational fundamentals of the programmable structures;
- state-machine design;
- languages for hardware definition;
- hardware design tool QUARTUS - advantes capabilities;
- advantes capabilities of the VERILOG language;
- application of the IP COREs;
- basics of the VHDL language;
- softcore systems;
- paralelization of the algorithms.
- Literature
- 2. Rafael C. Gonzales, Richar E. Woods: Digital Image Processing, Prentice Hall, ISBN 978-0-13-168728-8
- 3. HDL - Chip Design, Douglas J. Smith, ISBN 0-9651934-3-8
- Assessment methods
- Final examination consist from defence of the:
- set of tasks submitted during semester
- final project. - Language of instruction
- Czech
- Follow-Up Courses
- Further comments (probably available only in Czech)
- Study Materials
The course is taught annually.
PV200 Programable Structures
Faculty of InformaticsAutumn 2007
- Extent and Intensity
- 2/2. 4 credit(s) (plus extra credits for completion). Type of Completion: zk (examination).
- Teacher(s)
- RNDr. Vojtěch Krmíček, Ph.D. (seminar tutor)
doc. Mgr. Radek Pelánek, Ph.D. (assistant)
Ing. Zbyněk Bureš, Ph.D. (lecturer)
prof. Ing. Václav Přenosil, CSc. (lecturer) - Guaranteed by
- prof. Ing. Václav Přenosil, CSc.
Department of Machine Learning and Data Processing – Faculty of Informatics
Contact Person: prof. Ing. Václav Přenosil, CSc. - Timetable
- Mon 10:00–11:50 B411, Mon 16:00–17:50 B202
- Prerequisites
- Course PB161 - C++ programming is necessary for current course.
- Course Enrolment Limitations
- The course is also offered to the students of the fields other than those the course is directly associated with.
- fields of study / plans the course is directly associated with
- there are 37 fields of study the course is directly associated with, display
- Course objectives
- Programming and design tools of the programmable structures. VHDLand VERILOG languages.
- Syllabus
- Fundamentals of the programmable structures VHDL language VERILOG language
- Assessment methods (in Czech)
- Během semestru bude zadána samostaná práce, jejíž výsledky budou součástí závěrečného hodnocení. Závěrečné hodnocení má formu ústní zkoušky skložené ze tří částí: 1) obhajoba projektu zadaného pro samostanou práci, 2) vyřešení jednoduchého příkladu, 3) ústní odpověď na teoretickou otázku z přehledu témat ke zkoušce.
- Language of instruction
- Czech
- Follow-Up Courses
- Further comments (probably available only in Czech)
- The course is taught annually.
PV200 Computer Lexicography and Corpus Linguistics
Faculty of InformaticsAutumn 2002
- Extent and Intensity
- 3/2. (plus 1 credit for an exam). Type of Completion: zk (examination).
- Teacher(s)
- Dr. Patrick Hanks, Ph.D. (lecturer)
prof. PhDr. Karel Pala, CSc. (lecturer)
Mgr Pavel Rychly, Ph.D. (seminar tutor) - Guaranteed by
- prof. PhDr. Karel Pala, CSc.
Department of Machine Learning and Data Processing – Faculty of Informatics
Contact Person: prof. PhDr. Karel Pala, CSc. - Timetable
- Mon 10:00–12:50 B410, Tue 11:00–13:50 B204, Wed 10:00–12:50 B003, Thu 10:00–12:50 B003, Fri 10:00–12:50 B410
- Course Enrolment Limitations
- The course is also offered to the students of the fields other than those the course is directly associated with.
The capacity limit for the course is 25 student(s).
Current registration and enrolment status: enrolled: 0/25, only registered: 0/25, only registered with preference (fields directly associated with the programme): 0/25 - fields of study / plans the course is directly associated with
- there are 8 fields of study the course is directly associated with, display
- Language of instruction
- English
- Further Comments
- The course is taught only once.
PV200 Programable Structures
Faculty of InformaticsAutumn 2006
The course is not taught in Autumn 2006
- Extent and Intensity
- 2/2. 4 credit(s) (plus extra credits for completion). Type of Completion: zk (examination).
- Teacher(s)
- prof. Ing. Václav Přenosil, CSc. (lecturer)
- Guaranteed by
- prof. Ing. Václav Přenosil, CSc.
Department of Machine Learning and Data Processing – Faculty of Informatics - Prerequisites
- Course PB161 - C++ programming is necessary for current course.
- Course Enrolment Limitations
- The course is also offered to the students of the fields other than those the course is directly associated with.
- fields of study / plans the course is directly associated with
- Applied Informatics (programme FI, B-AP)
- Informatics (programme FI, B-IN)
- Course objectives
- Programming and design tools of the programmable structures. VHDLand VERILOG languages.
- Syllabus
- Fundamentals of the programmable structures VHDL language VERILOG language
- Assessment methods (in Czech)
- Během semestru bude zadána samostaná práce, jejíž výsledky budou součástí závěrečného hodnocení. Závěrečné hodnocení má formu ústní zkoušky skložené ze tří částí: 1) obhajoba projektu zadaného pro samostanou práci, 2) vyřešení jednoduchého příkladu, 3) ústní odpověď na teoretickou otázku z přehledu témat ke zkoušce.
- Language of instruction
- Czech
- Follow-Up Courses
- Further comments (probably available only in Czech)
- The course is taught annually.
The course is taught: every week.
- Enrolment Statistics (recent)