JONÁŠ, Martin and Jan STREJČEK. Speeding up Quantified Bit-Vector SMT Solvers by Bit-Width Reductions and Extensions. Online. In Luca Pulina and Martina Seidl. Theory and Applications of Satisfiability Testing - SAT 2020 - 23rd International Conference, Alghero, Italy, July 3-10, 2020, Proceedings. Cham (Switzerland): Springer, 2020, p. 378-393. ISBN 978-3-030-51824-0. Available from: https://dx.doi.org/10.1007/978-3-030-51825-7_27.
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Basic information
Original name Speeding up Quantified Bit-Vector SMT Solvers by Bit-Width Reductions and Extensions
Authors JONÁŠ, Martin (203 Czech Republic) and Jan STREJČEK (203 Czech Republic, guarantor, belonging to the institution).
Edition Cham (Switzerland), Theory and Applications of Satisfiability Testing - SAT 2020 - 23rd International Conference, Alghero, Italy, July 3-10, 2020, Proceedings, p. 378-393, 16 pp. 2020.
Publisher Springer
Other information
Original language English
Type of outcome Proceedings paper
Field of Study 10201 Computer sciences, information science, bioinformatics
Country of publisher Switzerland
Confidentiality degree is not subject to a state or trade secret
Publication form electronic version available online
WWW URL
Impact factor Impact factor: 0.402 in 2005
RIV identification code RIV/00216224:14330/20:00114392
Organization unit Faculty of Informatics
ISBN 978-3-030-51824-0
ISSN 0302-9743
Doi http://dx.doi.org/10.1007/978-3-030-51825-7_27
UT WoS 000711645300027
Keywords in English SMT solving; bit-vector logic; Boolector; Q3B
Tags bit-vector logic, core_A, firank_A, formela-conference, SMT solving
Tags International impact, Reviewed
Changed by Changed by: RNDr. Pavel Šmerk, Ph.D., učo 3880. Changed: 29/4/2021 12:29.
Abstract
Recent experiments have shown that satisfiability of a quantified bit-vector formula coming from practical applications almost never changes after reducing all bit-widths in the formula to a small number of bits. This paper proposes a novel technique based on this observation. Roughly speaking, a given quantified bit-vector formula is reduced and sent to a solver, an obtained model is then extended to the original bit-widths and verified against the original formula. We also present an experimental evaluation demonstrating that this technique can significantly improve the performance of state-of-the-art smt solvers Boolector, CVC4, and Q3B on quantified bit-vector formulas from the smt-lib repository.
Links
GA18-02177S, research and development projectName: Abstrakce a jiné techniky v semi-symbolické verifikaci programů
Investor: Czech Science Foundation
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