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@misc{559201,
author = {Holeček, Jan and Kratochvíla, Tomáš and Řehák, Vojtěch and Šafránek, David and Šimeček, Pavel},
address = {Praha},
keywords = {formal verification; programmable hardware; FPGA; Cadence SMV; VHDL},
language = {eng},
location = {Praha},
publisher = {CESNET, z.s.p.o.},
title = {How to Formalize FPGA Hardware Design},
url = {http://www.cesnet.cz/doc/techzpravy/2004/formal-fpga-design/},
year = {2004}
}
TY - GEN
ID - 559201
AU - Holeček, Jan - Kratochvíla, Tomáš - Řehák, Vojtěch - Šafránek, David - Šimeček, Pavel
PY - 2004
TI - How to Formalize FPGA Hardware Design
VL - CESNET Technical Report No. 04/2004
PB - CESNET, z.s.p.o.
CY - Praha
KW - formal verification
KW - programmable hardware
KW - FPGA
KW - Cadence SMV
KW - VHDL
UR - http://www.cesnet.cz/doc/techzpravy/2004/formal-fpga-design/
L2 - http://www.cesnet.cz/doc/techzpravy/2004/formal-fpga-design/
N2 - In this report, a formal view of an FPGA hardware design is presented. An approach of how elementary FPGA design entities can be modeled in terms of Kripke structures is presented here. The report is also focused on capturing the problems of modeling synchronous parts of hardware design together with its asynchronous parts.
ER -
HOLEČEK, Jan, Tomáš KRATOCHVÍLA, Vojtěch ŘEHÁK, David ŠAFRÁNEK a Pavel ŠIMEČEK. \textit{How to Formalize FPGA Hardware Design}. Praha: CESNET, z.s.p.o., 2004. CESNET Technical Report No. 04/2004.
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