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@inproceedings{630886, author = {Antoš, David and Řehák, Vojtěch and Holub, Petr}, address = {Prague}, booktitle = {CESNET Conference 2006 Proceedings}, keywords = {packet filtering; hardware accelerated routing; filtring rules transformation; filtering decision diagram; binary decision diagram}, language = {eng}, location = {Prague}, isbn = {80-239-6533-6}, pages = {161--173}, publisher = {CESNET, z. s. p. o.}, title = {Packet Filtering for FPGA-Based Routing Accelerator}, url = {http://www.ces.net/conference06/}, year = {2006} }
TY - JOUR ID - 630886 AU - Antoš, David - Řehák, Vojtěch - Holub, Petr PY - 2006 TI - Packet Filtering for FPGA-Based Routing Accelerator PB - CESNET, z. s. p. o. CY - Prague SN - 8023965336 KW - packet filtering KW - hardware accelerated routing KW - filtring rules transformation KW - filtering decision diagram KW - binary decision diagram UR - http://www.ces.net/conference06/ N2 - In this paper, we present a novel approach for Binary Decision Diagram based semantically extended representation of packet filters called Filter Decision Diagrams (FDD), used for efficient filter processing and lookup in a hardware accelerator that uses a lookup engine employing CAM and comparison instructions kept in SRAM. We present the most important operations for FDDs and also give some complexity estimate. We also analyze and compare expressing power of the most commonly available packet filters. ER -
ANTOŠ, David, Vojtěch ŘEHÁK a Petr HOLUB. Packet Filtering for FPGA-Based Routing Accelerator. In \textit{CESNET Conference 2006 Proceedings}. Prague: CESNET, z. s. p. o., 2006, s.~161--173. ISBN~80-239-6533-6.
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