PV200 Introduction to hardware description languages

Faculty of Informatics
Autumn 2019
Extent and Intensity
0/2/1. 3 credit(s) (plus extra credits for completion). Type of Completion: k (colloquium).
RNDr. Zdeněk Matěj, Ph.D. (lecturer)
RNDr. Ondřej Herman (seminar tutor)
prof. Ing. Václav Přenosil, CSc. (alternate examiner)
Guaranteed by
RNDr. Zdeněk Matěj, Ph.D.
Department of Computer Systems and Communications - Faculty of Informatics
Contact Person: prof. Ing. Václav Přenosil, CSc.
Supplier department: Department of Computer Systems and Communications - Faculty of Informatics
Timetable of Seminar Groups
PV200/01: Mon 14:00–15:50 A415, O. Herman, Z. Matěj
PV200/02: Thu 10:00–11:50 A415, O. Herman, Z. Matěj
Course Enrolment Limitations
The course is also offered to the students of the fields other than those the course is directly associated with.
fields of study / plans the course is directly associated with
there are 71 fields of study the course is directly associated with, display
Course objectives
Within this course the students will obtain deeper knowledge on the field of programmable structures (e.g. FPGAs) and get familiar with advanced methods of hardware design using hardware description languages. Verilog HDL is used to demonstrate most of the principles.
Learning outcomes
Graduates of this course will be able to:
understand the FPGA principle
understand the programming languages VHDL and Verilog
design advanced systems using HDL languages
program application for FPGA
  • Programmable structures fundamentals.
  • Verilog HDL – concepts, basic syntax, abstraction levels, design hierarchy.
  • Designing in Verilog – combinational primitives, sequential circuits, state machine design.
  • FPGA devices – capabilities, limitations, programming. Advanced features in Verilog, best practice.
  • Prefabricated components – IP cores, Megafunctions.
  • Interfaces & Peripherals – RS232, LCD, keyboard.
  • Introduction to VHDL.
  • Sofcore computing – introduction to NIOS2 processor system.
  • Practical tasks in Quartus II suite.
  • 3. HDL - Chip Design, Douglas J. Smith, ISBN 0-9651934-3-8
  • THOMAS, Donald E. and Philip R. MOORBY. The Verilog hardware description language. 5. ed. New York: Springer, 2002. xx, 381. ISBN 1402070896. info
Teaching methods
Laboratory seminar.
Assessment methods
Evaluation consists of: a) defense of set of tasks submitted during semester b) defense of final project.
Language of instruction
Follow-Up Courses
Further comments (probably available only in Czech)
Study Materials
The course is taught annually.
Teacher's information
The course is also listed under the following terms Autumn 2002, Autumn 2007, Autumn 2008, Autumn 2009, Autumn 2010, Autumn 2011, Autumn 2012, Autumn 2013, Autumn 2014, Autumn 2015, Autumn 2016, Autumn 2017, Autumn 2018.
  • Enrolment Statistics (recent)
  • Permalink: https://is.muni.cz/course/fi/autumn2019/PV200