Efficient On-Chip Randomness Testing Utilizing Machine Learning
Techniques.

J 2019

Efficient On-Chip Randomness Testing Utilizing Machine Learning Techniques.

MRAZEK, Vojtech, Lukas SEKANINA, Roland DOBAI, Marek SÝS, Petr ŠVENDA et. al.

Základní údaje

Originální název

Efficient On-Chip Randomness Testing Utilizing Machine Learning Techniques.

Autoři

MRAZEK, Vojtech, Lukas SEKANINA, Roland DOBAI, Marek SÝS (703 Slovensko, garant, domácí) a Petr ŠVENDA (203 Česká republika, domácí)

Vydání

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, IEEE, 2019, 1063-8210

Další údaje

Jazyk

angličtina

Typ výsledku

Článek v odborném periodiku

Obor

10201 Computer sciences, information science, bioinformatics

Stát vydavatele

Spojené státy

Utajení

není předmětem státního či obchodního tajemství

Odkazy

URL

Impakt faktor

Impact factor: 2.037

Kód RIV

RIV/00216224:14330/19:00107545

Organizační jednotka

Fakulta informatiky

DOI

http://dx.doi.org/10.1109/TVLSI.2019.2923848

UT WoS

000508360300004

Klíčová slova anglicky

Testing; Cryptography; Field programmable gate arrays; Hardware; System-on-chip; Generators; Machine learning

Příznaky

Mezinárodní význam, Recenzováno

Změněno: 28. 4. 2020 07:41, RNDr. Pavel Šmerk, Ph.D.

Anotace

V originále

Randomness testing is an important procedure that bit streams, produced by critical cryptographic primitives such as encryption functions and hash functions, have to undergo. In this paper, a new hardware platform for the randomness testing is proposed. The platform exploits the principles of genetic programming, which is a machine learning technique developed for the automated program and circuit design. The platform is capable of evolving efficient randomness distinguishers directly on a chip. Each distinguisher is represented as a Boolean polynomial in the algebraic normal form. The randomness testing is conducted for bit streams that are either stored in an on-chip memory or generated by a circuit placed on the chip. The platform is developed with a Xilinx Zynq-7000 All Programmable System on Chip that integrates a field programmable gate array with on-chip ARM processors. The platform is evaluated in terms of the quality of randomness testing, performance, and resources utilization. With power budget less than 3 W, the platform provides comparable randomness testing capabilities with the standard testing batteries running on a personal computer.

Návaznosti

GA16-08565S, projekt VaV

Název: Rozvoj kryptoanalytických metod prostřednictvím evolučních výpočtů

Investor: Grantová agentura ČR, Advancing cryptanalytic methods through evolutionary computing

Citovat

MRAZEK, Vojtech, Lukas SEKANINA, Roland DOBAI, Marek SÝS a Petr ŠVENDA. Efficient On-Chip Randomness Testing Utilizing Machine Learning Techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. IEEE, 2019, roč. 27, č. 12, s. 2734-2744. ISSN 1063-8210. Dostupné z: https://dx.doi.org/10.1109/TVLSI.2019.2923848.

@article{1548639,
   author = {MRAZEK, Vojtech and Sekanina, Lukas and Dobai, Roland and Sýs, Marek and Švenda, Petr},
   article_number = {12},
   doi = {http://dx.doi.org/10.1109/TVLSI.2019.2923848},
   keywords = {Testing; Cryptography; Field programmable gate arrays; Hardware; System-on-chip; Generators; Machine learning},
   language = {eng},
   issn = {1063-8210},
   journal = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
   title = {Efficient On-Chip Randomness Testing Utilizing Machine Learning Techniques.},
   url = {http://dx.doi.org/10.1109/TVLSI.2019.2923848},
   volume = {27},
   year = {2019}
}

TY  - JOUR
ID  - 1548639
AU  - MRAZEK, Vojtech - Sekanina, Lukas - Dobai, Roland - Sýs, Marek - Švenda, Petr
PY  - 2019
TI  - Efficient On-Chip Randomness Testing Utilizing Machine Learning Techniques.
JF  - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
VL  - 27
IS  - 12
SP  - 2734-2744
EP  - 2734-2744
PB  - IEEE
SN  - 10638210
KW  - Testing
KW  - Cryptography
KW  - Field programmable gate arrays
KW  - Hardware
KW  - System-on-chip
KW  - Generators
KW  - Machine learning
UR  - http://dx.doi.org/10.1109/TVLSI.2019.2923848
L2  - http://dx.doi.org/10.1109/TVLSI.2019.2923848
N2  - Randomness testing is an important procedure that bit streams, produced by critical cryptographic primitives such as encryption functions and hash functions, have to undergo. In this paper, a new hardware platform for the randomness testing is proposed. The platform exploits the principles of genetic programming, which is a machine learning technique developed for the automated program and circuit design. The platform is capable of evolving efficient randomness distinguishers directly on a chip. Each distinguisher is represented as a Boolean polynomial in the algebraic normal form. The randomness testing is conducted for bit streams that are either stored in an on-chip memory or generated by a circuit placed on the chip. The platform is developed with a Xilinx Zynq-7000 All Programmable System on Chip that integrates a field programmable gate array with on-chip ARM processors. The platform is evaluated in terms of the quality of randomness testing, performance, and resources utilization. With power budget less than 3 W, the platform provides comparable randomness testing capabilities with the standard testing batteries running on a personal computer.
ER  -

MRAZEK, Vojtech, Lukas SEKANINA, Roland DOBAI, Marek SÝS a Petr ŠVENDA. Efficient On-Chip Randomness Testing Utilizing Machine Learning Techniques. \textit{IEEE Transactions on Very Large Scale Integration (VLSI) Systems}. IEEE, 2019, roč.~27, č.~12, s.~2734-2744. ISSN~1063-8210. Dostupné z: https://dx.doi.org/10.1109/TVLSI.2019.2923848.

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