Efficient Code Region Characterization Through Automatic
Performance Counters Reduction Using Machine Learning
Techniques

D 2024

Efficient Code Region Characterization Through Automatic Performance Counters Reduction Using Machine Learning Techniques

HARUTYUNYAN, Suren; Eduardo CÉSAR; Anna SIKORA; Jiří FILIPOVIČ; Akash DUTTA et. al.

Základní údaje

Originální název

Efficient Code Region Characterization Through Automatic Performance Counters Reduction Using Machine Learning Techniques

Autoři

HARUTYUNYAN, Suren; Eduardo CÉSAR; Anna SIKORA; Jiří FILIPOVIČ; Akash DUTTA; Ali JANNESARI a Jordi ALCARAZ

Vydání

Madrid, Spain, European Conference on Parallel Processing, od s. 18-32, 15 s. 2024

Nakladatel

Springer Nature Switzerland

Další údaje

Jazyk

angličtina

Typ výsledku

Stať ve sborníku

Obor

10201 Computer sciences, information science, bioinformatics

Stát vydavatele

Španělsko

Utajení

není předmětem státního či obchodního tajemství

Forma vydání

elektronická verze "online"

Odkazy

URL

Impakt faktor

Impact factor: 0.402 v roce 2005

Kód RIV

RIV/00216224:14610/24:00137325

Organizační jednotka

Ústav výpočetní techniky

ISBN

978-3-031-69576-6

ISSN

DOI

https://doi.org/10.1007/978-3-031-69577-3_2

UT WoS

001308370000002

EID Scopus

2-s2.0-85202614939

Klíčová slova anglicky

Performance counters; Automatic dimension reduction; machine learning ensambles; parallel region classification

Štítky

core_B, rivok

Příznaky

Mezinárodní význam, Recenzováno

Změněno: 4. 4. 2025 13:13, Mgr. Eva Špillingová

Anotace

V originále

Leveraging hardware performance counters provides valuable insights into system resource utilization, aiding performance analysis and tuning for parallel applications. The available counters vary with architecture and are collected at execution time. Their abundance and the limited number of registers for measurement make gathering laborious and costly. Efficient characterization of parallel regions necessitates a dimension reduction strategy. While recent efforts have focused on manually reducing the number of counters for specific architectures, this paper introduces a novel approach: an automatic dimension reduction technique for efficiently characterizing parallel code regions across diverse architectures. The methodology is based on Machine Learning ensembles because of their precision and ability at capturing different relationships between the input features and the target variables. Evaluation results show that ensembles can successfully reduce the number of hardware performance counters that characterize a code region. We validate our approach on CPUs using a comprehensive dataset of OpenMP regions, showing that any region can be accurately characterized by 8 relevant hardware performance counters. In addition, we also apply the proposed methodology on GPUs using a reduced set of kernels, demonstrating its effectiveness across various hardware configurations and workloads.

Návaznosti

LM2023054, projekt VaV

Název: e-Infrastruktura CZ

Investor: Ministerstvo školství, mládeže a tělovýchovy ČR, e-Infrastruktura CZ

Citovat

HARUTYUNYAN, Suren; Eduardo CÉSAR; Anna SIKORA; Jiří FILIPOVIČ; Akash DUTTA; Ali JANNESARI a Jordi ALCARAZ. Efficient Code Region Characterization Through Automatic Performance Counters Reduction Using Machine Learning Techniques. Online. In Carretero, J; Shende, S; Garcia-Blas, J; Brandic I; Olcoz, K ; Schreiber, M. European Conference on Parallel Processing. Madrid, Spain: Springer Nature Switzerland, 2024, s. 18-32. ISBN 978-3-031-69576-6. Dostupné z: https://doi.org/10.1007/978-3-031-69577-3_2.

@inproceedings{2442223,
   author = {Harutyunyan, Suren and César, Eduardo and Sikora, Anna and Filipovič, Jiří and Dutta, Akash and Jannesari, Ali and Alcaraz, Jordi},
   address = {Madrid, Spain},
   booktitle = {European Conference on Parallel Processing},
   doi = {https://doi.org/10.1007/978-3-031-69577-3_2},
   editor = {Carretero, J; Shende, S; Garcia-Blas, J; Brandic I; Olcoz, K ; Schreiber, M},
   keywords = {Performance counters; Automatic dimension reduction; machine learning ensambles; parallel region classification},
   howpublished = {elektronická verze "online"},
   language = {eng},
   location = {Madrid, Spain},
   isbn = {978-3-031-69576-6},
   pages = {18-32},
   publisher = {Springer Nature Switzerland},
   title = {Efficient Code Region Characterization Through Automatic Performance Counters Reduction Using Machine Learning Techniques},
   url = {https://link.springer.com/chapter/10.1007/978-3-031-69577-3_2},
   year = {2024}
}

TY  - CONF
ID  - 2442223
AU  - Harutyunyan, Suren - César, Eduardo - Sikora, Anna - Filipovič, Jiří - Dutta, Akash - Jannesari, Ali - Alcaraz, Jordi
PY  - 2024
TI  - Efficient Code Region Characterization Through Automatic Performance Counters Reduction Using Machine Learning Techniques
PB  - Springer Nature Switzerland
CY  - Madrid, Spain
SN  - 9783031695766
KW  - Performance counters
KW  - Automatic dimension reduction
KW  - machine learning ensambles
KW  - parallel region classification
UR  - https://link.springer.com/chapter/10.1007/978-3-031-69577-3_2
N2  - Leveraging hardware performance counters provides valuable insights into system resource utilization, aiding performance analysis and tuning for parallel applications. The available counters vary with architecture and are collected at execution time. Their abundance and the limited number of registers for measurement make gathering laborious and costly. Efficient characterization of parallel regions necessitates a dimension reduction strategy. While recent efforts have focused on manually reducing the number of counters for specific architectures, this paper introduces a novel approach: an automatic dimension reduction technique for efficiently characterizing parallel code regions across diverse architectures. The methodology is based on Machine Learning ensembles because of their precision and ability at capturing different relationships between the input features and the target variables. Evaluation results show that ensembles can successfully reduce the number of hardware performance counters that characterize a code region. We validate our approach on CPUs using a comprehensive dataset of OpenMP regions, showing that any region can be accurately characterized by 8 relevant hardware performance counters. In addition, we also apply the proposed methodology on GPUs using a reduced set of kernels, demonstrating its effectiveness across various hardware configurations and workloads.
ER  -

HARUTYUNYAN, Suren; Eduardo CÉSAR; Anna SIKORA; Jiří FILIPOVIČ; Akash DUTTA; Ali JANNESARI a Jordi ALCARAZ. Efficient Code Region Characterization Through Automatic Performance Counters Reduction Using Machine Learning Techniques. Online. In Carretero, J; Shende, S; Garcia-Blas, J; Brandic I; Olcoz, K ; Schreiber, M. \textit{European Conference on Parallel Processing}. Madrid, Spain: Springer Nature Switzerland, 2024, s.~18-32. ISBN~978-3-031-69576-6. Dostupné z: https://doi.org/10.1007/978-3-031-69577-3\_{}2.

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