A 2003

Verification of COMBO6 VHDL Design

KRATOCHVÍLA, Tomáš, Vojtěch ŘEHÁK and Pavel ŠIMEČEK

Basic information

Original name

Verification of COMBO6 VHDL Design

Authors

KRATOCHVÍLA, Tomáš (203 Czech Republic), Vojtěch ŘEHÁK (203 Czech Republic, guarantor) and Pavel ŠIMEČEK (203 Czech Republic)

Edition

Praha, CESNET Technical Report No. 17/2003, 2003

Publisher

CESNET, z.s.p.o.

Other information

Language

English

Type of outcome

Audiovizuální tvorba

Field of Study

10201 Computer sciences, information science, bioinformatics

Country of publisher

Czech Republic

Confidentiality degree

není předmětem státního či obchodního tajemství

References:

RIV identification code

RIV/00216224:14330/03:00008325

Organization unit

Faculty of Informatics

Keywords in English

Liberouter; Combo6; formal verification; hardware verification; model checking; Cadence SMV; LeonardoSpectrum

Tags

Změněno: 18/10/2004 15:55, doc. RNDr. Vojtěch Řehák, Ph.D.

Abstract

V originále

This technical report presents current results and experiences of the formal verification of VHDL design of Combo6 hardware accelerator card. Information about formal verification itself is enriched by description of transformation from VHDL to the Cadence SMV specification language and the system of assertions established as a compact way of communication with VHDL designers.

Links

GA201/03/0509, research and development project
Name: Automatizovaná verifikace paralelních a distribuovaných systémů
Investor: Czech Science Foundation, Automated Verification of Parallel and Distributed Systems
MSM 000000001, plan (intention)
Name: Vysokorychlostní síť národního výzkumu a její nové aplikace
MSM 143300001, plan (intention)
Name: Nesekvenční modely výpočtů - kvantové a souběžné distribuované modely výpočetních procesů
Investor: Ministry of Education, Youth and Sports of the CR, Non-sequential Models of Computing -- Quantum and Concurrent Distributed Models of Computing