Automatic generation of circuits for approximate string matching

MARTÍNEK, Tomáš; Matej LEXA; Patrik BECK and Otto FUČÍK. Automatic generation of circuits for approximate string matching. In Proceedings of 2007 IEEE Design and Diagnostics of Electronic Circuits and Systems. Krakow: IEEE Computer Society, 2007, p. 203-208. ISBN 1-4244-1161-0.

Basic information

Original name

Automatic generation of circuits for approximate string matching

Name in Czech

Automatické generování obvodů pro přibližné vyhledávání v řetězcích

Authors

MARTÍNEK, Tomáš (203 Czech Republic); Matej LEXA (703 Slovakia, guarantor, belonging to the institution); Patrik BECK (703 Slovakia) and Otto FUČÍK (203 Czech Republic)

Edition

Krakow, Proceedings of 2007 IEEE Design and Diagnostics of Electronic Circuits and Systems, p. 203-208, 6 pp. 2007

Publisher

IEEE Computer Society

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Other information

Language

English

Type of outcome

Proceedings paper

Field of Study

20206 Computer hardware and architecture

Country of publisher

Czech Republic

Confidentiality degree

is not subject to a state or trade secret

RIV identification code

RIV/00216224:14330/07:00041393

Organization unit

Faculty of Informatics

ISBN

1-4244-1161-0

UT WoS

000250200100033

Keywords in English

Approximate string matching; systolic array architecture; FPGA; DNA sequence analysis

Tags

Approximate string matching, DNA sequence analysis, FPGA, systolic array architecture

Tags

International impact, Reviewed

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Abstract

V originále

Systolic array architectures for approximate string matching play a significant role as hardware accelerators in biological applications. However, their wider use is limited by the lack of flexibility required by often variable tasks. In this respect, it is desirable to develop a procedure for automatic design and implementation of such accelerators to reach high performance and efficiency with as little human effort on the side of the designer as possible. This paper describes such procedure.

In Czech

Architektury typu systolické pole pro porovnávání řetězců nalézají využití jako hardwarové akcelerátory v biologických aplikacích. Jejich širší využití naráží na potíže s flexibilitou konkrétních návrhů. V tomto článku popisujeme techniku návrhu takového akcelerátoru pro širokou skupinu problémů, která může značně odbřemenit návrháře obvodů.

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Links

MSM0021622419, plan (intention)

Name: Vysoce paralelní a distribuované výpočetní systémy Investor: Ministry of Education, Youth and Sports of the CR, Highly Parallel and Distributed Computing Systems