Fault Collapsing and Test Generation for a Circuit

@inproceedings{1125452,
   author = {Amiri, Moslem and Přenosil, Václav},
   address = {Brno, Czech Republic},
   booktitle = {Deterioration, Dependability, Diagnostics 2013},
   edition = {first},
   editor = {Jiří Stodola},
   keywords = {fault list generation; test vector generation; fault paths},
   howpublished = {tištěná verze "print"},
   language = {eng},
   location = {Brno, Czech Republic},
   isbn = {978-80-7231-939-8},
   pages = {55-61},
   publisher = {University of Defence},
   title = {Fault Collapsing and Test Generation for a Circuit},
   year = {2013}
}

TY  - JOUR
ID  - 1125452
AU  - Amiri, Moslem - Přenosil, Václav
PY  - 2013
TI  - Fault Collapsing and Test Generation for a Circuit
PB  - University of Defence
CY  - Brno, Czech Republic
SN  - 9788072319398
KW  - fault list generation
KW  - test vector generation
KW  - fault paths
N2  - A novel method to generate a complete list of faults and their corresponding test vectors for a gate-level circuit is presented. This method creates the distinguishable faults of a circuit based on the paths they propagate, along with the test vector(s) for each fault. While the other available methods for fault list and test vector generation are expensive, this method tries to reduce the cost by avoiding all the unnecessary steps and merging the two tasks together.
ER  - 

AMIRI, Moslem a Václav PŘENOSIL. Fault Collapsing and Test Generation for a Circuit. In Jiří Stodola. \textit{Deterioration, Dependability, Diagnostics 2013}. first. Brno, Czech Republic: University of Defence, 2013, s.~55-61. ISBN~978-80-7231-939-8.