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@misc{561408, author = {Holeček, Jan and Kratochvíla, Tomáš and Řehák, Vojtěch and Šafránek, David and Šimeček, Pavel}, address = {Praha}, keywords = {formal verification; Liberouter; Cadence SMV; VHDL}, language = {eng}, location = {Praha}, publisher = {CESNET z.s.p.o.}, title = {Verification Process of Hardware Design in Liberouter Project}, url = {http://www.cesnet.cz/doc/techzpravy/2004/verifprocess/}, year = {2004} }
TY - GEN ID - 561408 AU - Holeček, Jan - Kratochvíla, Tomáš - Řehák, Vojtěch - Šafránek, David - Šimeček, Pavel PY - 2004 TI - Verification Process of Hardware Design in Liberouter Project VL - CESNET Technical Report No. 05/2004 PB - CESNET z.s.p.o. CY - Praha KW - formal verification KW - Liberouter KW - Cadence SMV KW - VHDL UR - http://www.cesnet.cz/doc/techzpravy/2004/verifprocess/ L2 - http://www.cesnet.cz/doc/techzpravy/2004/verifprocess/ N2 - This technical report analyzes the process of verification of hardware design in Liberouter project. Such an analysis had become a necessity since we had developed several tools that were difficult both to maintain and modify. This document tries to sum up our needs and to propose a way our tools could be organized. Description of verification environment Verunka is given in more detail as it is a new tool. ER -
HOLEČEK, Jan, Tomáš KRATOCHVÍLA, Vojtěch ŘEHÁK, David ŠAFRÁNEK and Pavel ŠIMEČEK. \textit{Verification Process of Hardware Design in Liberouter Project}. Praha: CESNET z.s.p.o., 2004. CESNET Technical Report No. 05/2004.
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