Physical security threats appear at the chip level, where an attacker can measure or physically influence a cryptographic operation performed by the chip's circuit. The side-channel analysis exploits additional sources of information (called physical observations), including timing, power consumption, or electromagnetic emissions (EM), among others. Malicious data modifications can be caused by fault injection, which can be performed using optical, electromagnetic, power, and clock glitches. These attacks pose a serious threat to modern cryptographic implementations.

The goal of the thesis is to propose a methodology for assessing the resistance of cryptographic libraries against fault injection attacks. The assessment process will utilize an existing fault injection simulator to validate the library's behavior under fault conditions. The first task will be to review existing fault-injection simulators and select a suitable one (i.e., efficient and recently developed). Based on the literature review, a model of the attacker's capabilities will be established, against which the libraries will be evaluated. The proposed methodology will then be applied to at least three open-source libraries designed for embedded devices that implement the Elliptic Curve Diffie-Hellman (ECDH) key establishment protocol. The libraries shall be assessed against multiple common fault injection attacks, as discovered during the literature review. The presented results will clearly indicate which fault injection attacks the evaluated libraries are susceptible to. Lastly, the thesis will propose, implement, and validate countermeasures for at least one of the discovered vulnerabilities.

The tasks within the projects are divided into approximately 60% programming/prototyping and 40% literature study.