Physical security threats appear at the chip level, where an attacker can measure or physically influence a cryptographic operation performed by the chip's circuit. In particular, malicious data modifications can be caused by fault injection, which can be performed using optical, electromagnetic, power, and clock glitches. These attacks pose a severe threat to modern cryptographic implementations.

The goal of this topic is to evaluate the fault-injection resistance of a new Trezor crypto wallet built by SatoshiLabs, one of the leading manufacturers of crypto wallets. The SatoshiLabs company will provide us with two development boards that the student will use to test the fault injection resistance of the processor. The processor is identical to the one that is used in the new release of the Trezor crypto wallet. 

We would like to note that the processor in the scope of this thesis is the main STM32 CPU of the Trezor crypto wallet and not its secure element. The following board will be used for the fault-injection tests: https://www.st.com/en/evaluation-tools/stm32u5a9j-dk.html

The fault injection experiments will be executed using ChipWhisperer-Husky which is in possession of the CRoCS lab; the documentation for that device is under the following link: https://rtfm.newae.com/Capture/ChipWhisperer-Husky/

Two types of fault-injections experiments are in the scope of the project:
- power voltage glitching (for which only Husky is necessary) and
- electromagnetic fault injection for which the setup uses both Husky and ChipSHOUTER-PicoEMP
fault-injection probe (https://github.com/newaetech/chipshouter-picoemp). 

The division of the tasks within the project is approximately: 40% prototyping and programming, 45% lab work, and 15% literature study.