PV172 Digital Computer Architecture

Faculty of Informatics
Spring 2009
Extent and Intensity
2/2. 4 credit(s) (plus extra credits for completion). Type of Completion: zk (examination).
prof. Ing. Václav Přenosil, CSc. (lecturer)
Ing. Zbyněk Bureš, Ph.D. (seminar tutor)
RNDr. Vojtěch Krmíček, Ph.D. (seminar tutor)
Guaranteed by
prof. Ing. Václav Přenosil, CSc.
Department of Machine Learning and Data Processing - Faculty of Informatics
Tue 8:00–9:50 B410, Tue 10:00–11:50 B202
Course PV170 - Design of Digital Computersis is advisable source of necessary knowledges for current course.
Course Enrolment Limitations
The course is also offered to the students of the fields other than those the course is directly associated with.
The capacity limit for the course is 30 student(s).
Current registration and enrolment status: enrolled: 0/30, only registered: 0/30, only registered with preference (fields directly associated with the programme): 0/30
fields of study / plans the course is directly associated with
there are 37 fields of study the course is directly associated with, display
Course objectives
Main aim of this courese is understand and master theoretical knowledges necessary for design high-performance digital systems. The lessons are specialized in particular into following topics:
application of the fundamental design components;
principle of the modular systems design metodology;
principle of the external devices connecting.
  • rchitecture of the digital systems;
  • structure of processors, CISC and RISC structures;
  • bus subsystem of the digital systems;
  • memory subsystem of the digital systems;
  • input and output subsystem the digital systems;
  • linkage hardware and operation system the digital systems;
  • external busses subsystem;
  • external memory subsystems;
  • design systems and simulations systems of digital systems.
  • ŠNOREK, RICHTA. Připojování periférií k PC
  • HLAVIČKA, J. Computer architecture. Praha: ČVUT, 1999
  • DOUŠA, J., PLUHÁČEK, V. Introduction to computer systems. Praha: ČVUT, 2000
Assessment methods
Final examination consist from 3 parts:
1) defence of the project - implementation of the design from laboratory lessons and discussion about protocol;
2) design of the circuit and verification of the design by laboratory tools;
3) oral exam - teoretical problems from list of the passed subjects.
Language of instruction
Follow-Up Courses
Further comments (probably available only in Czech)
Study Materials
The course is taught annually.
The course is also listed under the following terms Spring 2006, Spring 2007, Spring 2008, Spring 2010, Spring 2011, Spring 2012, Spring 2013, Spring 2014, Spring 2015, Spring 2016, Spring 2017, Spring 2018, Spring 2019, Spring 2020.
  • Enrolment Statistics (Spring 2009, recent)
  • Permalink: https://is.muni.cz/course/fi/spring2009/PV172